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tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A revision: v1.00 date: ?a??? 1?? ?01? ?a??? 1?? ?01?
rev. 1.00 ? ?a??? 1?? ?01? rev. 1.00 ? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom table of contents eates cpu featu?es ......................................................................................................................... 6 pe?ip?e?al featu?es ................................................................................................................. 6 gene?al des??iption ......................................................................................... 7 sele?tion table ................................................................................................. 7 blo?k diag?am .................................................................................................. 8 pin assignment ................................................................................................ ? pin des??iption .............................................................................................. 1? absolute ?aximum ratings .......................................................................... ?4 d.c. c?a?a?te?isti?s ....................................................................................... ?5 a.c. c?a?a?te?isti?s ....................................................................................... ?8 lvd & lvr ele?t?i?al c?a?a?te?isti?s .......................................................... ?? lcd d.c. c?a?a?te?isti?s .............................................................................. ?0 powe?-on reset c?a?a?te?isti?s ................................................................... ?1 system a???ite?tu?e ...................................................................................... ?1 clo?king and pipelining ......................................................................................................... ?1 p?og?am counte? ................................................................................................................... ?? sta?k ..................................................................................................................................... ?? a?it?meti? and logi? unit C alu ........................................................................................... ?? flas? p?og?am ?emo?y ................................................................................. ?4 st?u?tu?e ................................................................................................................................ ?4 spe? ial ve?to?s ..................................................................................................................... ?5 look-up table ........................................................................................................................ ?5 table p ?og?am example ........................................................................................................ ?5 in ci??uit p?og?amming C icp ............................................................................................... ?6 on-c?ip debug suppo?t C ocds ......................................................................................... ?7 data ?emo?y .................................................................................................. ?8 st?u?tu?e ................................................................................................................................ ?8 gene?al pu?pose data ?emo?y ............................................................................................ ?? spe?ial pu?pose data ?emo?y ............................................................................................. ?? spe?ial fun?tion registe? des??iption ........................................................ 4? indi?e? t add?essing registe?s C iar0? iar1 ......................................................................... 4? ?emo?y pointe?s C ?p0? ?p1 .............................................................................................. 4? bank pointe? C bp ................................................................................................................. 44 a??umulato? C acc ............................................................................................................... 45 p?og?am counte? low registe? C pcl .................................................................................. 45 look-up table registe ? s C tblp ? tbhp ? tblh ..................................................................... 45 status registe? C status .................................................................................................... 46
rev. 1.00 ? ?a??? 1?? ?01? rev. 1.00 ? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom eeprom data memory .................................................................................. 48 eepro? registe?s .............................................................................................................. 48 reading data f?om t?e eepro? ......................................................................................... 50 w ?iting data to t?e eepro? ................................................................................................ 50 w ?ite p?ote?tion ..................................................................................................................... 50 eepro? inte??upt ................................................................................................................ 50 p?og?amming conside?ations ................................................................................................ 51 oscillator ........................................................................................................ 52 os?illato? ove?view ............................................................................................................... 5? system clock confgurations ................................................................................................ 5? exte?nal c?ystal/ce?ami? os?illato? C hxt ........................................................................... 5? exte?nal rc os?illato? C erc ............................................................................................... 54 inte?nal rc os?illato? C hirc ............................................................................................... 54 exte?nal ??.768khz c?ystal os?illato? C lxt ........................................................................ 55 lxt os ?illato? low powe? fun?tion ...................................................................................... 56 inte?nal ??khz os?illato? C lirc ........................................................................................... 56 exte?nal clo?k C ec .............................................................................................................. 56 supplementa?y os?illato?s .................................................................................................... 56 operating modes and system clocks ......................................................... 57 system clo?k ........................................................................................................................ 57 system ope?ation ?odes ...................................................................................................... 58 cont?ol registe? .................................................................................................................... 5? fast wake-up ........................................................................................................................ 61 ope?ating ?ode swit??ing .................................................................................................... 61 ope?ating ?ode swit?? ing and wake-up .............................................................................. 6? nor? al ?ode to slow ?ode swit??ing ........................................................................... 6? slow ?ode to nor? al ?ode swit??ing ........................................................................... 64 ente?ing t?e sleep0 ?ode .................................................................................................. 65 ente?ing t?e sleep1 ?ode .................................................................................................. 65 ente?ing t?e idle0 ?ode ...................................................................................................... 65 ente?ing t?e idle1 ?ode ...................................................................................................... 66 standby cu??ent conside?ations ........................................................................................... 66 wake-up ................................................................................................................................ 67 p?og?amming conside?ations ................................................................................................ 67 watchdog timer ............................................................................................. 68 wat ?? dog time? clo?k sou??e .............................................................................................. 68 wat ?? dog time? cont?ol registe? ......................................................................................... 68 wat ?? dog time? ope?ation ................................................................................................... 6? reset and initialisation .................................................................................. 70 reset fun?tions .................................................................................................................... 71 reset initial conditions ......................................................................................................... 74
rev. 1.00 4 ?a??? 1?? ?01? rev. 1.00 5 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom input/output ports ......................................................................................... 78 i/o po?t registe? list ............................................................................................................. 78 pull-?ig? resisto?s ................................................................................................................ 81 po? t a wake-up ..................................................................................................................... 81 i/o po?t cont?ol registe?s ..................................................................................................... 81 pin-s?a?ed fun?tions ............................................................................................................ 81 i/o pin st?u?tu?es .................................................................................................................. ?? p?og?amming conside?ations ................................................................................................ ?? timer modules C tm ...................................................................................... 93 int?odu?tion ........................................................................................................................... ?? t? ope?ation ........................................................................................................................ ?? t? clo?k sou??e ................................................................................................................... ?4 t? inte??upts ......................................................................................................................... ?4 t? exte?nal pins ................................................................................................................... ?4 t? input/output pin cont?ol registe?s ................................................................................. ?5 p?og?amming conside?ations .............................................................................................. 101 compact type tm C ctm ............................................................................ 102 compa?t t? ope?ation ....................................................................................................... 10? compa? t type t? registe? des??iption .............................................................................. 10? compa? t type t? ope?ating ?odes .................................................................................. 107 compa?e ?at?? output ?ode ............................................................................................. 107 time ?/counte? ?ode ............................................................................................................ 110 pw? output ?ode ............................................................................................................... 110 standard type tm C stm ............................................................................. 113 standa?d t? ope?ation ........................................................................................................ 11 ? standa? d type t? registe? des??iption .............................................................................. 114 standa? d type t? ope?ating ?odes .................................................................................. 1?? compa?e output ?ode ........................................................................................................ 1?? time ?/counte? ?ode ........................................................................................................... 1?6 pw? output ?ode .............................................................................................................. 1?6 single pulse ?ode .............................................................................................................. 1?0 captu?e input ?ode ............................................................................................................ 1?? enhanced type tm C etm ........................................................................... 134 en?an? ed t? ope?ation ..................................................................................................... 1?4 en?an? ed type t? registe? des??iption ............................................................................ 1?5 en?an? ed type t? ope?ating ?odes ................................................................................. 14? compa?e output ?ode ........................................................................................................ 14? time ?/counte? ?ode ........................................................................................................... 147 pw? output ?ode .............................................................................................................. 147 single pulse output ?ode .................................................................................................. 15? captu?e input ?ode ............................................................................................................ 155
rev. 1.00 4 ?a??? 1?? ?01? rev. 1.00 5 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom interrupts ...................................................................................................... 158 inte??upt registe?s ............................................................................................................... 158 inte??upt ope?ation .............................................................................................................. 164 exte?nal inte??upt ................................................................................................................. 166 ?ulti-fun?tion inte??upt ........................................................................................................ 166 time base inte ??upt ............................................................................................................. 167 eepro? inte??upt .............................................................................................................. 168 lvd inte ??upt ....................................................................................................................... 168 t? inte??upts ....................................................................................................................... 168 inte?? upt wake-up fun?tion ................................................................................................. 16? p?og?amming conside?ations .............................................................................................. 16? low voltage detector C lvd ....................................................................... 170 lvd registe ? ....................................................................................................................... 170 lvd ope ?ation ..................................................................................................................... 171 lcd driver .................................................................................................... 172 lcd ?emo?y ....................................................................................................................... 17? lcd registe? ....................................................................................................................... 174 lcd reset fun?tion ............................................................................................................ 175 clo?k sou??e ....................................................................................................................... 175 lcd d?ive? output ............................................................................................................... 175 lcd voltage sou ??e biasing ............................................................................................... 176 lcd wavefo ? m timing diag?am .......................................................................................... 177 p?og?amming conside?ations .............................................................................................. 18? confguration options ................................................................................. 183 application circuits ..................................................................................... 184 instruction set .............................................................................................. 185 int?odu?tion ......................................................................................................................... 185 inst?u? tion timing ................................................................................................................ 185 ? oving and t ?ansfe??ing data ............................................................................................. 185 a?it?meti? ope?ations .......................................................................................................... 185 logi?al and rotate ope?ations ............................................................................................ 186 b?an??es and cont? ol t ?ansfe? ........................................................................................... 186 bit ope?ations ..................................................................................................................... 186 table read ope ?ations ....................................................................................................... 186 ot?e? ope?ations ................................................................................................................. 186 instruction set summary ............................................................................ 187 table ?onventions ............................................................................................................... 187 instruction defnition ................................................................................... 189 package information ................................................................................... 198 48-pin lqfp (7mm7mm) outline dimensions .................................................................. 1?? 64-pin lqfp (7mm7mm) outline dimensions .................................................................. ?00 80-pin lqfp (10mm10mm) outline dimensions .............................................................. ?01
rev. 1.00 6 ?a??? 1?? ?01? rev. 1.00 7 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom features cpu features ? operating voltage: f sys = 4mhz: 2.2v~5.5v f sys = 8mhz: 2.4v~5.5v f sys =12mhz: 2.7v~5.5v f sys =20mhz: 4.5v~5.5v ? up to 0.2s instruction cycle with 20mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? oscillator types: external crystal C hxt external 32.765khz crystal C lxt external rc C erc external clock C ec internal rc C hirc internal 32khz rc C lirc ? multi-mode operation: normal, slow, idle and sleep ? fully integrated internal 4mhz, 8mhz and 12mhz oscillator requires no external components ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? up to 8-level subroutine nesting ? bit manipulation instruction peripheral features ? flash program memory: 2k16~8k16 ? data memory: 1288~3848 ? eeprom memory: 648~1288 ? watchdog timer function ? up to 52 bidirectional i/o lines ? lcd driver function ? multiple pin-shared external interrupts ? multiple timer module for time measure, input capture, compare match output, pwm output or single pulse output function ? dual time-base functions for generation of fxed time interrupt signals ? low voltage reset function ? low voltage detect function ? wide range of available package types
rev. 1.00 6 ?a??? 1?? ?01? rev. 1.00 7 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom general description the ht69fx0a series of devices are flash memory lcd type 8-bit high performance risc architecture microcontrollers, designed for applications which require an lcd interface. offering users the convenience of flash memory multi-programming features, these devices also include a wide range of functions and features. other memory includes an area of ram data memory. analog features include multiple and extremely flexible timer modules provide timing, pulse generation and pwm generation functions. protective features such as an internal watchdog timer, low voltage reset and low voltage detector coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of internal and external oscillator functions are provided including fully integrated low and high speed system oscillators which requires no external components for their implementation. the ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. the inclusion of fexible i/o programming features, time-base functions along with many other features ensure that the devices will fnd excellent use in applications such as consumer products, handheld instruments, household appliances, electronically controlled tools and motor driving in addition to many others. selection table most features are common to all devices. the main features distinguishing them are memory capacity, i/o count, tm features, stack capacity, lcd driver and package types. the following table summarises the main features of each device. part no. program memory data memory data eeprom i/o external interrupt lcd driver timer module time base stacks package ht6?f?0a ?k16 1?88 648 ?? ? ?44 ?5? 10-bit ct?1 10-bit st?1 ? 4 48lqfp ht6?f40a 4k16 ?568 1?88 51 ? ?64 ?7? 10-bit ct?1 10-bit st?1 10-bit et?1 ? 8 48/64lqfp ht6?f50a 8k16 ?848 1?88 6? ? 484 4?? 10-bit ct?1 16-bit st?1 10-bit et?1 ? 8 48/64/80lqfp note: as devices exist in more than one package format, the table refects the situation for the package with the most pins.
rev. 1.00 8 ?a??? 1?? ?01? rev. 1.00 ? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom block diagram flash/eeprom programming circuitry (icp)/ocds watchdog timer 8-bit risc mcu core reset circuit interrupt controller erc/ec/hxt oscillator lirc/lxt oscillator hirc oscillator stack eeprom data memory flash program memory ram data memory tm0 tmn low voltage reset low voltage detect time base i/o lcd driver tm1
rev. 1.00 8 ?a??? 1?? ?01? rev. 1.00 ? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pin assignment ht69f30a 48 lqfp-a 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 pa6/tp0_0 pa5/tp1_1 pa4/int0 pa3/tp1_0 pa2/tck0/tck1 pa0/int1 pa1/tp0_1 pb1/osc2 pb0/osc1 vdd vss pb2/xt1 pa7/res pd0/seg0/int1 pd1/seg1/tck0 pd2/seg2/tck1 pd3/seg3 pd4/seg4 pd5/seg5 pd6/seg6 pd7/seg7 pe0/seg8 pe1/seg9 pe2/seg10 pb3/xt2 vlcd vmax v1 pc0/v2 pc1/c1 pc2/c2 com0 com1 com2 com3/seg24 pf7/seg23 pe3/seg11 pe4/seg12 pe5/seg13 pe6/seg14 pe7/seg15 pf0/seg16 pf1/seg17 pf2/seg18 pf3/seg19 pf4/seg20 pf5/seg21 pf6/seg22 ht69f30a 48 lqfp- a ht69f40a 48 lqfp-a 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 pa6/tp0_0 pa5/tp2_1 pa4/int0 pa3/tp2_0 pa2/tck0/tck2 pa0/int1/tck1 pa1/tp0_1 pb1/osc2 pb0/osc1 vdd vss pb2/xt1 pa7/res pd0/seg0/int1 pd1/seg1/tck0 pd2/seg2/tck2 pd3/seg3/tck1 pd4/seg4/tp1a pd5/seg5/tp1b_0 pd6/seg6/tp1b_1 pd7/seg7/tp1b_2 pe0/seg8 pe1/seg9 pe2/seg10 pb3/xt2 vlcd vmax v1 pc0/v2 pc1/c1 pc2/c2 com0 com1 com2 com3/seg24 pf7/seg23 pe3/seg11 pe4/seg12 pe5/seg13 pe6/seg14 pe7/seg15 pf0/seg16 pf1/seg17 pf2/seg18 pf3/seg19 pf4/seg20 pf5/seg21 pf6/seg22 ht69f40a 48 lqfp- a
rev. 1.00 10 ?a??? 1?? ?01? rev. 1.00 11 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f40a 64 lqfp-a 1 2 3 4 5 6 7 8 9 10 11 12 13 20 21 22 23 24 25 26 27 28 60 61 62 63 64 29 30 31 32 52 53 54 55 56 57 58 59 14 15 16 43 44 45 46 47 48 36 37 38 39 40 41 42 33 34 35 17 18 19 49 50 51 pb3/xt2 vlcd vmax v1 pc0/v2 pc1/c1 pc2/c2 com0 com1 com2 com3/seg36 seg35 seg34 seg33 seg32 pg7/seg31 pa7/res pd0/seg0/int1 pd1/seg1/tck0 pd2/seg2/tck2 pd3/seg3/tck1 pd4/seg4/tp1a pd5/seg5/tp1b_0 pd6/seg6/tp1b_1 pd7/seg7/tp1b_2 pe0/seg8 pe1/seg9 pe2/seg10 pe3/seg11 pe4/seg12 pe5/seg13 pe6/seg14 pe7/seg15 pf0/seg16 pf1/seg17 pf2/seg18 pf3/seg19 pf4/seg20 pf5/seg21 pf6/seg22 pf7/seg23 pg0/seg24 pg1/seg25 pg2/seg26 pg3/seg27 pg4/seg28 pg5/seg29 pg6/seg30 pa6/tp0_0 pa5/tp2_1 pa4/int0 pa3/tp2_0 pa2/tck0/tck2 pa0/int1/tck1 pa1/tp0_1 pb1/osc2 pb7/tp1b_2 pb6/tp1b_1 pb5/tp1b_0 pb4/tp1a pb0/osc1 vdd vss pb2/xt1 ht69f40a 64 lqfp- a HT69F50A 48 lqfp-a 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 pa6/tp0_0 pa5/tp2_1 pa4/int0 pa3/tp2_0 pa2/tck0/tck2 pa0/int1/tck1 pa1/tp0_1 pb1/osc2 pb0/osc1 vdd vss pb2/xt1 pa7/res pd0/seg0/int1 pd1/seg1/tck0 pd2/seg2/tck2 pd3/seg3/tck1 pd4/seg4/tp1a pd5/seg5/tp1b_0 pd6/seg6/tp1b_1 pd7/seg7/tp1b_2 pe0/seg8 pe1/seg9 pe2/seg10 pb3/xt2 plcd vmax v1 pc0/v2 pc1/c1 pc2/c2 com0 com1 com2 com3/seg24 pf7/seg23 pe3/seg11 pe4/seg12 pe5/seg13 pe6/seg14 pe7/seg15 pf0/seg16 pf1/seg17 pf2/seg18 pf3/seg19 pf4/seg20 pf5/seg21 pf6/seg22 HT69F50A 48 lqfp- a
rev. 1.00 10 ?a??? 1?? ?01? rev. 1.00 11 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom HT69F50A 64 lqfp-a 1 2 3 4 5 6 7 8 9 10 11 12 13 20 21 22 23 24 25 26 27 28 60 61 62 63 64 29 30 31 32 52 53 54 55 56 57 58 59 14 15 16 43 44 45 46 47 48 36 37 38 39 40 41 42 33 34 35 17 18 19 49 50 51 pb3/xt2 plcd vmax v1 pc0/v2 pc1/c1 pc2/c2 com0 com1 com2 com3/seg36 ph3/seg35 ph2/seg34 ph1/seg33 ph0/seg32 pg7/seg31 pa7/res pd0/seg0/int1 pd1/seg1/tck0 pd2/seg2/tck2 pd3/seg3/tck1 pd4/seg4/tp1a pd5/seg5/tp1b_0 pd6/seg6/tp1b_1 pd7/seg7/tp1b_2 pe0/seg8 pe1/seg9 pe2/seg10 pe3/seg11 pe4/seg12 pe5/seg13 pe6/seg14 pe7/seg15 pf0/seg16 pf1/seg17 pf2/seg18 pf3/seg19 pf4/seg20 pf5/seg21 pf6/seg22 pf7/seg23 pg0/seg24 pg1/seg25 pg2/seg26 pg3/seg27 pg4/seg28 pg5/seg29 pg6/seg30 pa6/tp0_0 pa5/tp2_1 pa4/int0 pa3/tp2_0 pa2/tck0/tck2 pa0/int1/tck1 pa1/tp0_1 pb1/osc2 pb7/tp1b_2 pb6/tp1b_1 pb5/tp1b_0 pb4/tp1a pb0/osc1 vdd vss pb2/xt1 HT69F50A 64 lqfp- a 47 46 45 44 43 42 41 HT69F50A 80 lqf p-a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 40 49 48 pa6/tp0_0 pa5/tp2_1 pa4/int0 pa3/tp2_0 pa2/tck0/tck2 pa0/int1/tck1 pa1/tp0_1 pb1/osc2 pb7/tp1b_2 pb6/tp1b_1 pb5/tp1b_0 pb4/tp1a pb0/osc1 vdd pc3 pc4 pc5 pc6 vss pb2/xt1 pa7/res pd0/seg0/int1 pd1/seg1/tck0 pd2/seg2/tck2 pd3/seg3/tck1 pd4/seg4/tp1a pd5/seg5/tp1b_0 pd6/seg6/tp1b_1 pd7/seg7/tp1b_2 pe0/seg8 pe1/seg9 pe2/seg10 pe3/seg11 pe4/seg12 pe5/seg13 pe6/seg14 pe7/seg15 pf0/seg16 pf1/seg17 pf2/seg18 pb3/xt2 vlcd vmax v1 pc0/v2 pc1/c1 pc2/c2 com0 com1 com2 com3/seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 ph7/seg39 pf3/seg19 pf4/seg20 pf5/seg21 pf6/seg22 pf7/seg23 pg0/seg24 pg1/seg25 pg2/seg26 pg3/seg27 pg4/seg28 pg5/seg29 pg6/seg30 pg7/seg31 ph0/seg32 ph1/seg33 ph2/seg34 ph3/seg35 ph4/seg36 ph5/seg37 ph6/seg38 HT69F50A 80 lqfp- a
rev. 1.00 1? ?a??? 1?? ?01? rev. 1.00 1? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom 47 46 45 44 43 42 41 ht69v50a 80 lqf p-a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 40 49 48 pa6/tp0_0 pa5/tp2_1 pa4/int0 pa3/tp2_0 pa2/tck0/tck2/icpck/ocdsck pa0/int1/tck1/icpda/ocdsda pa1/tp0_1 pb1/osc2 pb7/tp1b_2 pb6/tp1b_1 pb5/tp1b_0 pb4/tp1a pb0/osc1 vdd pc3 pc4 pc5 pc6 vss pb2/xt1 pa7/res pd0/seg0/int1 pd1/seg1/tck0 pd2/seg2/tck2 pd3/seg3/tck1 pd4/seg4/tp1a pd5/seg5/tp1b_0 pd6/seg6/tp1b_1 pd7/seg7/tp1b_2 pe0/seg8 pe1/seg9 pe2/seg10 pe3/seg11 pe4/seg12 pe5/seg13 pe6/seg14 pe7/seg15 pf0/seg16 pf1/seg17 pf2/seg18 pb3/xt2 vlcd vmax v1 pc0/v2 pc1/c1 pc2/c2 com0 com1 com2 com3/seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 ph7/seg39 pf3/seg19 pf4/seg20 pf5/seg21 pf6/seg22 pf7/seg23 pg0/seg24 pg1/seg25 pg2/seg26 pg3/seg27 pg4/seg28 pg5/seg29 pg6/seg30 pg7/seg31 ph0/seg32 ph1/seg33 ph2/seg34 ph3/seg35 ph4/seg36 ph5/seg37 ph6/seg38 ht69v50a 80 lqfp- a note: 1. if the pin-shared pin functions have multiple outputs simultaneously, the output function is determined by the corresponding software control bits except the functions determined by the confguration options. 2. the ht69v50a device is the ev chip of the ht69fx0a series of devices. it supports the on-chip debug function for debugging during development using the ocdsda and ocdsck pins connected to the holtek ht-ide development tools.
rev. 1.00 1? ?a??? 1?? ?01? rev. 1.00 1? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pin description ht69f30a pad name function opt i/t o/t description pa0/int1/icpda /ocdsda pa0 pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up int1 integ intc0 sfs st exte?nal inte??upt 1 icpda st c?os icp data/add ?ess ocdsda st c?os ocds data/add?ess pa1/tp0_1 pa1 pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up tp0_1 pafs st c?os t?0 i/o pin pa ?/tck0/tck1 /icpck/ocdsck pa ? pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up tck0 sfs st t?0 input tck1 sfs st t?1 input icpck st c?os icp clo ?k pin ocdsck st ocds clo?k pin pa ?/tp1_0 pa ? pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up tp1_0 pafs st c?os t?1 i/o pin pa4/int0 pa4 papu pawu st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up int0 integ intc0 st exte?nal inte??upt 0 pa5/tp1_1 pa5 pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up tp1_1 pafs st c?os t?1 i/o pin pa6/tp0_0 pa6 pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up tp0_0 pafs st c?os t?0 i/o pin pa7/ res pa7 pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up res co st reset pin pb0/osc1 pb0 pbpu st c?os gene?al pu?pose i/o. registe? enabled pull-up osc1 co hxt hxt/erc os?illato? pin & ec mode input pin pb1/osc? pb1 pbpu st c?os gene?al pu?pose i/o. registe? enabled pull-up osc? co hxt hxt os ?illato? pin pb?/xt1 pb? pbpu st c?os gene?al pu?pose i/o. registe? enabled pull-up xt1 co lxt lxt os ?illato? pin pb?/xt? pb? pbpu st c?os gene?al pu?pose i/o. registe? enabled pull-up xt? co lxt lxt os ?illato? pin
rev. 1.00 14 ?a??? 1?? ?01? rev. 1.00 15 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pad name function opt i/t o/t description pc0/v? pc0 pcpu pcfs st c?os gene?al pu?pose i/o. registe? enabled pull-up v? pcfs ao lcd voltage pump pc1/c1 pc1 pcpu pcfs st c?os gene?al pu?pose i/o. registe? enabled pull-up c1 pcfs ao lcd voltage pump pc?/c? pc? pcpu pcfs st c?os gene?al pu?pose i/o. registe? enabled pull-up c? pcfs ao lcd voltage pump pd0/seg0/int1 pd0 pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg0 pdfs ao lcd segment output int1 integ intc0 sfs st exte?nal inte??upt 1 pd1/seg1/tck0 pd1 pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg1 pdfs ao lcd segment output tck0 sfs st t?0 input pd?/seg?/tck1 pd? pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg? pdfs ao lcd segment output tck1 sfs st t?1 input pd?/seg? pd? pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg? pdfs ao lcd segment output pd4/seg4 pd4 pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg4 pdfs ao lcd segment output pd5/seg5 pd5 pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg5 pdfs ao lcd segment output pd6/seg6 pd6 pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg6 pdfs ao lcd segment output pd7/seg7 pd7 pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg7 pdfs ao lcd segment output pe0/seg8 pe0 pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg8 pefs ao lcd segment output pe1/seg? pe1 pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg? pefs ao lcd segment output pe?/seg10 pe? pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg10 pefs ao lcd segment output pe? /seg11 pe? pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg11 pefs ao lcd segment output
rev. 1.00 14 ?a??? 1?? ?01? rev. 1.00 15 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pad name function opt i/t o/t description pe4/seg1? pe4 pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg1? pefs ao lcd segment output pe5/seg1? pe5 pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg1? pefs ao lcd segment output pe6/seg14 pe6 pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg14 pefs ao lcd segment output pe7/seg15 pe7 pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg15 pefs ao lcd segment output pf0/seg16 pf0 pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg16 pffs ao lcd segment output pf1/seg17 pf1 pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg17 pffs ao lcd segment output pf?/seg18 pf? pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg18 pffs ao lcd segment output pf?/seg1? pf? pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg1? pffs ao lcd segment output pf4/seg?0 pf4 pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?0 pffs ao lcd segment output pf5/seg?1 pf5 pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?1 pffs ao lcd segment output pf6/seg?? pf6 pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?? pffs ao lcd segment output pf7/seg?? pf7 pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?? pffs ao lcd segment output co?0~co?? co?n ao lcd ?ommon outputs co??/seg?4 co?? ao lcd ?ommon output seg?4 lcdc ao lcd segment output v1 v1 ao lcd voltage pump vlcd vlcd pwr lcd powe? supply v?ax v?ax pwr ic maximum voltage? ?onne?ted to vdd? vlcd o? v1 vdd vdd pwr positive powe? supply vss vss pwr negative powe? supply. g?ound note: i/t: input type; o/t: output type opt: optional by confguration option (co) or register option pwr: power; co: confguration option st: schmitt trigger input; ao: analog output cmos: cmos output; nmos: nmos output hxt: high frequency crystal oscillator lxt: high frequency crystal oscillator
rev. 1.00 16 ?a??? 1?? ?01? rev. 1.00 17 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f40a pad name function opt i/t o/t description pa0/int1 /tck1/icpda /ocdsda pa0 pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up int1 integ intc0 sfs st exte?nal inte??upt 1 tck1 sfs st t?1 input icpda st c?os icp data/add ?ess ocdsda st c?os ocds data/add?ess pa1/tp0_1 pa1 pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up tp0_1 pafs st c?os t?0 i/o pin pa ?/tck0 /tck?/icpck /ocdsck pa ? pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up tck0 sfs st t?0 input tck? sfs st t?? input icpck st c?os icp clo ?k pin ocdsck st ocds clo?k pin pa ?/tp?_0 pa ? pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up tp?_0 pafs st c?os t?? i/o pin pa4/int0 pa4 papu pawu st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up int0 integ intc0 st exte?nal inte??upt 0 pa5/tp ?_1 pa5 pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up tp?_1 pafs st c?os t?? i/o pin pa6/tp0_0 pa6 pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up tp0_0 pafs st c?os t?0 i/o pin pa7/ res pa7 pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up res co st reset pin pb0/osc1 pb0 pbpu st c?os gene?al pu?pose i/o. registe? enabled pull-up osc1 co hxt hxt/erc os?illato? pin & ec mode input pin pb1/osc? pb1 pbpu st c?os gene?al pu?pose i/o. registe? enabled pull-up osc? co hxt hxt os ?illato? pin pb?/xt1 pb? pbpu st c?os gene?al pu?pose i/o. registe? enabled pull-up xt1 co lxt lxt os ?illato? pin pb?/xt? pb? pbpu st c?os gene?al pu?pose i/o. registe? enabled pull-up xt? co lxt lxt os ?illato? pin pb4/tp1a pb1 pbpu pbfs st c?os gene?al pu?pose i/o. registe? enabled pull-up tp1a pbfs st c?os t?1 i/o pin
rev. 1.00 16 ?a??? 1?? ?01? rev. 1.00 17 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pad name function opt i/t o/t description pb5/tp1b_0 pb5 pbpu pbfs st c?os gene?al pu?pose i/o. registe? enabled pull-up tp1b_0 pbfs st c?os t?1 i/o pin pb6/tp1b_1 pb6 pbpu pbfs st c?os gene?al pu?pose i/o. registe? enabled pull-up tp1b_1 pbfs st c?os t?1 i/o pin pb7/tp1b_? pb7 pbpu pbfs st c?os gene?al pu?pose i/o. registe? enabled pull-up tp1b_? pbfs st c?os t?1 i/o pin pc0/v? pc0 pcpu pcfs st c?os gene?al pu?pose i/o. registe? enabled pull-up v? pcfs ao lcd voltage pump pc1/c1 pc1 pcpu pcfs st c?os gene?al pu?pose i/o. registe? enabled pull-up c1 pcfs ao lcd voltage pump pc?/c? pc? pcpu pcfs st c?os gene?al pu?pose i/o. registe? enabled pull-up c? pcfs ao lcd voltage pump pd0/seg0/int1 pd0 pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up. seg0 pdfs ao lcd segment output int1 integ intc0 sfs st exte?nal inte??upt 1 pd1/seg1/tck0 pd1 pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg1 pdfs ao lcd segment output tck0 sfs st t?0 input pd?/seg?/tck? pd? pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg? pdfs ao lcd segment output tck? sfs st t?? input pd?/seg?/tck1 pd? pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg? pdfs ao lcd segment output tck1 sfs st t?1 input pd4/seg4/tp1a pd4 pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg4 pdfs sfs ao lcd segment output tp1a pdfs sfs st c?os t?1 i/o pin pd5/seg5 /tp1b_0 pd5 pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg5 pdfs sfs ao lcd segment output tp1b_0 pdfs sfs st c?os t?1 i/o pin
rev. 1.00 18 ?a??? 1?? ?01? rev. 1.00 1? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pad name function opt i/t o/t description pd6/seg6 /tp1b_1 pd6 pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg6 pdfs sfs ao lcd segment output tp1b_1 pdfs sfs st c?os t?1 i/o pin pd7/seg7 /tp1b_? pd7 pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg7 pdfs sfs ao lcd segment output tp1b_? pdfs sfs st c?os t?1 i/o pin pe0/seg8 pe0 pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg8 pefs ao lcd segment output pe1/seg? pe1 pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg? pefs ao lcd segment output pe?/seg10 pe? pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg10 pefs ao lcd segment output pe? /seg11 pe? pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg11 pefs ao lcd segment output pe4/seg1? pe4 pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg1? pefs ao lcd segment output pe5/seg1? pe5 pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg1? pefs ao lcd segment output pe6/seg14 pe6 pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg14 pefs ao lcd segment output pe7/seg15 pe7 pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg15 pefs ao lcd segment output pf0/seg16 pf0 pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg16 pffs ao lcd segment output pf1/seg17 pf1 pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg17 pffs ao lcd segment output pf?/seg18 pf? pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg18 pffs ao lcd segment output pf?/seg1? pf? pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg1? pffs ao lcd segment output pf4/seg?0 pf4 pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?0 pffs ao lcd segment output
rev. 1.00 18 ?a??? 1?? ?01? rev. 1.00 1? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pad name function opt i/t o/t description pf5/seg?1 pf5 pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?1 pffs ao lcd segment output pf6/seg?? pf6 pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?? pffs ao lcd segment output pf7/seg?? pf7 pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?? pffs ao lcd segment output pg0/seg?4 pg0 pgpu pgfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?4 pgfs ao lcd segment output pg1/seg?5 pg1 pgpu pgfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?5 pgfs ao lcd segment output pg?/seg?6 pg? pgpu pgfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?6 pgfs ao lcd segment output pg?/seg?7 pg? pgpu pgfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?7 pgfs ao lcd segment output pg4/seg?8 pg4 pgpu pgfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?8 pgfs ao lcd segment output pg5/seg?? pg5 pgpu pgfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?? pgfs ao lcd segment output pg6/seg?0 pg6 pgpu pgfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?0 pgfs ao lcd segment output pg7/seg?1 pg7 pgpu pgfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?1 pgfs ao lcd segment output seg??~seg?5 segn ao lcd segment outputs co?0~co?? co?n ao lcd ?ommon outputs co??/seg?6 co?? ao lcd ?ommon output seg?6 lcdc ao lcd segment output v1 v1 ao lcd voltage pump vlcd vlcd pwr lcd powe? supply v?ax v?ax pwr ic maximum voltage? ?onne?ted to vdd? vlcd o? v1 vdd vdd pwr positive powe? supply vss vss pwr negative powe? supply. g?ound note: i/t: input type; o/t: output type opt: optional by confguration option (co) or register option pwr: power; co: confguration option st: schmitt trigger input; ao: analog output cmos: cmos output; nmos: nmos output hxt: high frequency crystal oscillator lxt: high frequency crystal oscillator
rev. 1.00 ?0 ?a??? 1?? ?01? rev. 1.00 ?1 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom HT69F50A pad name function opt i/t o/t description pa0/int1 /tck1/icpda /ocdsda pa0 pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up int1 integ intc0 sfs st exte?nal inte??upt 1 tck1 sfs st t?1 input icpda st c?os icp data/add ?ess ocdsda st c?os ocds data/add?ess pa1/tp0_1 pa1 pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up tp0_1 pafs st c?os t?0 i/o pin pa ?/tck0 /tck?/icpck /ocdsck pa ? pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up tck0 sfs st t?0 input tck? sfs st t?? input icpck st c?os icp clo ?k pin ocdsck st ocds clo?k pin pa ?/tp?_0 pa ? pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up tp?_0 pafs st c?os t?? i/o pin pa4/int0 pa4 papu pawu st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up int0 integ intc0 st exte?nal inte??upt 0 pa5/tp ?_1 pa5 pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up tp?_1 pafs st c?os t?? i/o pin pa6/tp0_0 pa6 pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up tp0_0 pafs st c?os t?0 i/o pin pa7/ res pa7 pawu papu pafs st c?os gene?al pu?pose i/o. registe? enabled pull-up and wake-up res co st reset pin pb0/osc1 pb0 pbpu st c?os gene?al pu?pose i/o. registe? enabled pull-up osc1 co hxt hxt/erc os?illato? pin & ec mode input pin pb1/osc? pb1 pbpu st c?os gene?al pu?pose i/o. registe? enabled pull-up osc? co hxt hxt os ?illato? pin pb?/xt1 pb? pbpu st c?os gene?al pu?pose i/o. registe? enabled pull-up xt1 co lxt lxt os ?illato? pin pb?/xt? pb? pbpu st c?os gene?al pu?pose i/o. registe? enabled pull-up xt? co lxt lxt os ?illato? pin pb4/tp1a pb1 pbpu pbfs st c?os gene?al pu?pose i/o. registe? enabled pull-up tp1a pbfs st c?os t?1 i/o pin
rev. 1.00 ?0 ?a??? 1?? ?01? rev. 1.00 ?1 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pad name function opt i/t o/t description pb5/tp1b_0 pb5 pbpu pbfs st c?os gene?al pu?pose i/o. registe? enabled pull-up tp1b_0 pbfs st c?os t?1 i/o pin pb6/tp1b_1 pb6 pbpu pbfs st c?os gene?al pu?pose i/o. registe? enabled pull-up tp1b_1 pbfs st c?os t?1 i/o pin pb7/tp1b_? pb7 pbpu pbfs st c?os gene?al pu?pose i/o. registe? enabled pull-up tp1b_? pbfs st c?os t?1 i/o pin pc0/v? pc0 pcpu pcfs st c?os gene?al pu?pose i/o. registe? enabled pull-up v? pcfs ao lcd voltage pump pc1/c1 pc1 pcpu pcfs st c?os gene?al pu?pose i/o. registe? enabled pull-up c1 pcfs ao lcd voltage pump pc?/c? pc? pcpu pcfs st c?os gene?al pu?pose i/o. registe? enabled pull-up c? pcfs ao lcd voltage pump pc?~pc6 pcn pcpu st c?os gene?al pu?pose i/o. registe? enabled pull-up pd0/seg0/int1 pd0 pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg0 pdfs ao lcd segment output int1 integ intc0 sfs st exte?nal inte??upt 1 pd1/seg1/tck0 pd1 pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg1 pdfs ao lcd segment output tck0 sfs st t?0 input pd?/seg?/tck? pd? pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg? pdfs ao lcd segment output tck? sfs st t?? input pd?/seg?/tck1 pd? pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg? pdfs ao lcd segment output tck1 sfs st t?1 input pd4/seg4/tp1a pd4 pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg4 pdfs sfs ao lcd segment output tp1a pdfs sfs st c?os t?1 i/o pin pd5/seg5 /tp1b_0 pd5 pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg5 pdfs sfs ao lcd segment output tp1b_0 pdfs sfs st c?os t?1 i/o pin
rev. 1.00 ?? ?a??? 1?? ?01? rev. 1.00 ?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pad name function opt i/t o/t description pd6/seg6 /tp1b_1 pd6 pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg6 pdfs sfs ao lcd segment output tp1b_1 pdfs sfs st c?os t?1 i/o pin pd7/seg7 /tp1b_? pd7 pdpu pdfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg7 pdfs sfs ao lcd segment output tp1b_? pdfs sfs st c?os t?1 i/o pin pe0/seg8 pe0 pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg8 pefs ao lcd segment output pe1/seg? pe1 pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg? pefs ao lcd segment output pe?/seg10 pe? pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg10 pefs ao lcd segment output pe? /seg11 pe? pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg11 pefs ao lcd segment output pe4/seg1? pe4 pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg1? pefs ao lcd segment output pe5/seg1? pe5 pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg1? pefs ao lcd segment output pe6/seg14 pe6 pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg14 pefs ao lcd segment output pe7/seg15 pe7 pepu pefs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg15 pefs ao lcd segment output pf0/seg16 pf0 pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg16 pffs ao lcd segment output pf1/seg17 pf1 pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg17 pffs ao lcd segment output pf?/seg18 pf? pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg18 pffs ao lcd segment output pf?/seg1? pf? pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg1? pffs ao lcd segment output pf4/seg?0 pf4 pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?0 pffs ao lcd segment output
rev. 1.00 ?? ?a??? 1?? ?01? rev. 1.00 ?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pad name function opt i/t o/t description pf5/seg?1 pf5 pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?1 pffs ao lcd segment output pf6/seg?? pf6 pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?? pffs ao lcd segment output pf7/seg?? pf7 pfpu pffs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?? pffs ao lcd segment output pg0/seg?4 pg0 pgpu pgfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?4 pgfs ao lcd segment output pg1/seg?5 pg1 pgpu pgfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?5 pgfs ao lcd segment output pg?/seg?6 pg? pgpu pgfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?6 pgfs ao lcd segment output pg?/seg?7 pg? pgpu pgfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?7 pgfs ao lcd segment output pg4/seg?8 pg4 pgpu pgfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?8 pgfs ao lcd segment output pg5/seg?? pg5 pgpu pgfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?? pgfs ao lcd segment output pg6/seg?0 pg6 pgpu pgfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?0 pgfs ao lcd segment output pg7/seg?1 pg7 pgpu pgfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?1 pgfs ao lcd segment output ph0/seg?? ph0 phpu phfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?? phfs ao lcd segment output ph1/seg?? ph1 phpu phfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?? phfs ao lcd segment output ph?/seg?4 ph? phpu phfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?4 phfs ao lcd segment output ph?/seg?5 ph? phpu phfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?5 phfs ao lcd segment output ph4/seg?6 ph4 phpu phfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?6 phfs ao lcd segment output ph5/seg?7 ph5 phpu phfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?7 phfs ao lcd segment output
rev. 1.00 ?4 ?a??? 1?? ?01? rev. 1.00 ?5 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pad name function opt i/t o/t description ph6/seg?8 ph6 phpu phfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?8 phfs ao lcd segment output ph7/seg?? ph7 phpu phfs st c?os gene?al pu?pose i/o. registe? enabled pull-up seg?? phfs ao lcd segment output seg40~seg47 segn ao lcd segment outputs co?0~co?? co?n ao lcd ?ommon outputs co??/seg48 co?? ao lcd ?ommon output seg48 lcdc ao lcd segment output v1 v1 ao lcd voltage pump vlcd vlcd pwr lcd powe? supply v?ax v?ax pwr ic maximum voltage? ?onne?ted to vdd? vlcd o? v1 vdd vdd pwr positive powe? supply vss vss pwr negative powe? supply. g?ound note: i/t: input type; o/t: output type opt: optional by confguration option (co) or register option pwr: power; co: confguration option st: schmitt trigger input; ao: analog output cmos: cmos output; nmos: nmos output hxt: high frequency crystal oscillator lxt: high frequency crystal oscillator absolute maximum ratings supply voltage ................................................................................................ v ss -0.3v to v ss +6.0v input voltage .................................................................................................. v ss -0.3v to v dd +0.3v i ol total .................................................................................................... 80ma total power dissipation ........................................................................................................ 500mw storage temperature .................................................................................................. -50 c to 125c operating temperature ................................................................................................ -40 c to 85 c i oh total .................................................................................................. -80ma note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
rev. 1.00 ?4 ?a??? 1?? ?01? rev. 1.00 ?5 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom d.c. characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd1 ope? ating voltage (hxt) f sys =4?hz ?.? 5.5 v f sys =8?hz ?.? 5.5 v f sys =1??hz ?.7 5.5 v f sys =16?hz 4.5 5.5 v v dd? ope? ating voltage (erc) f sys =4?hz ?.? 5.5 v f sys =8?hz ?.4 5.5 v f sys =1??hz ?.7 5.5 v f sys =16?hz 4.5 5.5 v f sys =?0?hz 4.5 5.5 v v dd? ope? ating voltage (hirc) f sys =4?hz ?.? 5.5 v f sys =8?hz ?.? 5.5 v f sys =1??hz ?.7 5.5 v i dd1 ope?ating cu??ent (hxt ? f sys =f h ? f s =f sub =f rtc o? f lirc ) ?v no load? f h =455khz? wdt enable 100 150 a 5v ?80 450 a ?v no load? f h =1?hz? wdt enable ?50 400 a 5v 500 1000 a ?v no load? f h =4?hz? wdt enable 450 700 a 5v 1000 1500 a ?v no load? f h =8?hz? wdt enable 0.8 1.5 ma 5v 1.5 ?.0 ma ?v no load? f h =1??hz? wdt enable 1.5 ?.5 ma 5v ?.0 5.0 ma 5v no load? f h =16?hz? wdt enable 4.0 6.0 ma i dd? ope?ating cu??ent (erc? f sys =f h ? f s =f sub =f rtc o? f lirc ) ?v no load? f h =455khz? wdt enable 66 110 a 5v ?00 ?00 a ?v no load? f h =1?hz? wdt enable ?50 400 a 5v 500 1000 a ?v no load? f h =4?hz? wdt enable 450 700 a 5v 1000 1500 a ?v no load? f h =8?hz? wdt enable 0.8 1.5 ma 5v 1.5 ?.0 ma ?v no load? f h =1??hz? wdt enable 1.5 ?.5 ma 5v ?.0 5.0 ma 5v no load? f h =16?hz? wdt enable 4.0 6.0 ma i dd? ope?ating cu??ent (hirc osc? f sys =f h ? f s =f sub =f rtc o? f lirc ) ?v no load? f h =4?hz? wdt enable 4?0 6?0 a 5v 700 1000 a ?v no load? f h =8?hz? wdt enable 0.8 1.5 ma 5v 1.5 ?.0 ma ?v no load? f h =1??hz? wdt enable 1.5 ?.5 ma 5v ?.0 5.0 ma i dd4 ope?ating cu??ent (ec? f sys =f h ? f s =f sub =f rtc o? f lirc ) ?v no load? f h =4?hz? wdt enable ??0 500 a 5v 550 8?0 a
rev. 1.00 ?6 ?a??? 1?? ?01? rev. 1.00 ?7 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom symbol parameter test conditions min. typ. max. unit v dd conditions i dd5 ope?ating cu??ent (hxt ? f sys =f l ? f s =f sub =f rtc o? f lirc ) ?v no load? f h =8?hz? f l =f h /?? wdt enable 500 750 a 5v 800 1?00 a ?v no load? f h =8?hz? f l =f h /4? wdt enable 4?0 6?0 a 5v 700 1000 a ?v no load? f h =8?hz? f l =f h /8? wdt enable 400 600 a 5v 600 800 a ?v no load? f h =8?hz? f l =f h /16? wdt enable ?60 540 a 5v 560 700 a ?v no load? f h =8?hz? f l =f h /??? wdt enable ??0 480 a 5v 5?0 650 a ?v no load? f h =8?hz? f l =f h /64? wdt enable ?80 4?0 a 5v 440 600 a i dd6 ope?ating cu??ent (hxt ? f sys =f l ? f s =f sub =f rtc o? f lirc ) ?v no load? f h =4?hz? f l =f h /?? wdt enable ?70 400 a 5v no load? f h =4?hz? f l =f h /?? wdt enable 560 840 a ?v no load? f h =4?hz? f l =f h /4? wdt enable 180 ?70 a 5v no load? f h =4?hz? f l =f h /4? wdt enable 400 600 a i dd7 ope?ating cu??ent (hxt ? f sys =f l ? f s =f sub =f rtc o? f lirc ) ?v no load? f h =1??hz? f l =f h /?? wdt enable 0.? 1.5 ma 5v no load? f h =1??hz? f l =f h /?? wdt enable 1.8 ?.7 ma ?v no load? f h =1??hz? f l =f h /4? wdt enable 0.6 1.0 ma 5v no load? f h =1??hz? f l =f h /4? wdt enable 0.? 1.4 ma i dd8 ope?ating cu??ent (lxt ? f sys =f l =f rtc ? f s =f sub =f rtc ) (ht6?f?0a? ht6?f40a) ?v no load? wdt enable? qosc=0 10 ?0 a 5v ?0 ?5 a ?v no load? wdt enable? qosc=1 10 ?0 a 5v ?0 ?5 a i dd8a ope?ating cu??ent (lxt ? f sys =f l =f rtc ? f s =f sub =f rtc ) (ht6?f50a) ?v no load? wdt enable? qosc=0 10 ?0 a 5v ?0 50 a ?v no load? wdt enable? qosc=1 10 ?0 a 5v ?0 50 a i dd? ope?ating cu??ent (lirc? f sys =f l =f lirc ? f s =f sub =f lirc ) (ht6?f?0a? ht6?f40a) ?v no load? wdt enable 10 ?0 a 5v ?0 ?5 a i dd?a ope?ating cu??ent (lirc? f sys =f l =f lirc ? f s =f sub =f lirc ) (ht6?f50a) ?v no load? wdt enable 10 ?0 a 5v ?0 50 a i dd10 ope?ating cu??ent (lxt o ? lirc? f sys =f l =f sub ) (ht6?f?0a? ht6?f40a) ?v no load? wdt enable? qosc=0 10 ?0 a 5v ?0 ?5 a i dd10a ope?ating cu??ent (lxt o ? lirc? f sys =f l =f sub ) (ht6?f50a) ?v no load? wdt enable? qosc=0 10 ?0 a 5v ?0 50 a i stb1 standby cu??ent (idle1) (hxt ? f sys =f h ? f s =f sub =f rtc o? f lirc ) ?v no load? system halt ? wdt enable? f sys =8?hz? fsyson=1 0.? 0.5 a 5v 0.5 0.8 a i stb? standby cu??ent (idle0) (hxt ? f sys =off ? f s =f sub =f rtc o? f lirc ) ?v no load? system halt ? wdt enable? f sys =8?hz? lxtlp=1 1.5 ?.0 a 5v ?.5 5.0 a i stb? standby cu??ent (idle0) (hirc? f sys =off ? f s =f sub =f lirc ) ?v no load? system halt ? wdt enable? f sys =8?hz 1.5 ?.0 a 5v ?.5 5.0 a
rev. 1.00 ?6 ?a??? 1?? ?01? rev. 1.00 ?7 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom symbol parameter test conditions min. typ. max. unit v dd conditions i stb4 standby cu??ent (idle0.) (hirc? f sys =off ? f s =f sub =f lirc ) ?v no load? system halt ? wdt enable? f sys =??768hz? lxtlp=1 1.5 ?.0 a 5v ?.5 5.0 a i stb5 standby cu??ent (idle0) (lxt ? f sys =off) ?v no load? system halt ? wdt enable? f sys =??768hz 1.5 ?.0 a 5v ?.5 5.0 a i stb6 standby cu??ent (idle0) (f sys =f l =f rtc ? f s =f sub =f rtc ) ?v no load? system halt ? wdt enable? f sys =??768hz? lxtlp=1 1.? 4.0 a 5v ?.? 7.0 a i stb7 standby cu??ent (idle) (lirc? f sys =off ? f s =f sub =f lirc ) ?v no load? system halt ? wdt enable? f sys =??khz 1.5 ?.0 a 5v ?.5 5.0 a i stb8 standby cu??ent (sleep0) (hxt ? f sys =off ? f s =f sub =f rtc o? f lirc ) ?v no load? system halt ? wdt disable? f sys =1??hz? lxtlp=1 0.1 1 a 5v 0.? ? a i stb? standby cu??ent (sleep1) (hxt ? f sys =off ? f s =f sub =f rtc ) ?v no load? system halt ? wdt enable? f sys =1??hz 1.5 ?.0 a 5v ?.5 5.0 a i stb10 standby cu??ent (sleep1) (hxt ? f sys =off ? f s =f sub =f lirc ) ?v no load? system halt ? wdt enable? f sys =1??hz 1.5 ?.0 a 5v ?.5 5.0 a i stb11 standby cu??ent (sleep0) (lxt ? f sys =off ? f s =f sub =f rtc ) ?v no load? system halt ? wdt disable? f sys =??768hz 0.1 1 a 5v 0.? ? a i stb1? standby cu??ent (sleep1) (lxt ? f sys =off ? f s =f sub =f rtc ) ?v no load? system halt ? wdt enable? f sys =??768hz? lxtlp=1 1.5 ?.0 a 5v ?.5 5.0 a v il1 input low voltage fo ? pa? pb? pc? pd? pe? pf ? tckn and intn 5 0v 1.5v v 0v 0.?v dd v v ih1 input hig? voltage fo? pa? pb? pc? pd? pe? pf ? tckn and intn 5 ?.5v 5v v 0.8v dd v dd v v il? input low voltage ( res ) 0 0.4v dd v v ih? input hig? voltage ( res ) 0.?v dd v dd v i ol i/o po?t sink cu??ent ?v v ol =0.1v dd 4 8 ma 5v v ol =0.1v dd 10 ?0 ma i oh i/o po?t sou??e cu??ent ?v v oh =0.?v dd -? -4 ma 5v v oh =0.?v dd -5 -10 ma r ph pull-?ig? resistan?e of i/o po?ts ?v ?0 60 100 k 5v 10 ?0 50 k
rev. 1.00 ?8 ?a??? 1?? ?01? rev. 1.00 ?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom a.c. characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd condition f cpu ope?ating clo?k ?.?~5.5v dc 4 ?hz ?.4~5.5v dc 8 ?hz ?.7~5.5v dc 1? ?hz 4.5~5.5v dc 16 ?hz f sys system ?lo?k (hxt) ?.?v~5.5v 0.4 4 ?hz ?.?v~5.5v 0.4 8 ?hz ?.7v~5.5v 0.4 1? ?hz 4.5v~5.5v 0.4 16 ?hz f hirc system ?lo?k (hirc) ?v/5v ta= ?5c -?% 4 +?% ?hz ?v/5v ta= ?5c -?% 8 +?% ?hz 5v ta= ?5c -?% 1? +?% ?hz ?.?v~?.6v ta=-40c~85c -8% 4 +8% ?hz ?.0v~5.5v ta=-40c~85c -8% 4 +8% ?hz ?.?v~?.6v ta=-40c~85c -8% 8 +8% ?hz ?.0v~5.5v ta=-40c~85c -8% 8 +8% ?hz ?.0v~5.5v ta=-40c~85c -8% 1? +8% ?hz f erc system ?lo?k (erc) 5v ta= ?5c exte?nal r erc =150k -?% 4 +?% ?hz 5v ta=0 c ~70c exte?nal r erc =150k -5% 4 +5% ?hz 5v ta=-40 c ~85c exte?nal r erc =150k -7% 4 +7% ?hz ?.0v~5.5v ta=-40 c ~85c exte?nal r erc =150k -?% 4 +?% ?hz ?.?v~5.5v ta=-40 c ~85c exte?nal r erc =150k -1?% 4 +1?% ?hz f lxt system clo?k (lxt) ??768 hz f lirc system clo?k (lirc) 5v ta= ?5c -10% ?? +10% khz ?.?v~5.5v ta=-40c~85c -50% ?? +60% khz t ti?er tckn and time? ?aptu?e input pulse widt? 0.? s t res exte?nal reset low pulse widt? 10 s t int inte??upt pulse widt? 10 s t sst system sta? t-up time? pe?iod (wake-up f ? om halt ? f sys off at halt state, slow modenormal mode, normal modeslow mode) f sys =hxt o ? lxt (slow ?ode no?mal ?ode(hxt)? no?mal ?ode slow ?ode(lxt)) 10?4 t sys f sys =hxt o ? lxt (wake-up f ? om halt ? f sys off at halt state) 10?4 t sys f sys =erc o? hirc 16 t sys f sys =lirc o? ec ? t sys system sta? t-up time? pe?iod (wake-up f ? om halt ? f sys on at halt state) ? t sys
rev. 1.00 ?8 ?a??? 1?? ?01? rev. 1.00 ?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom symbol parameter test conditions min. typ. max. unit v dd condition t rstd system reset delay time (powe? on reset? lvr ?eset? lvr s/w ? eset (lvrc)? wdt s/w ?eset (wdtc)) ?5 50 100 ms system reset delay time ( res ?eset? wdt no?mal ?eset) 8.? 16.7 ??.? ms t bgs v bg tu?n on stable time 10 ms t eerd eepro? read time 1 ? 4 t sys t eewr eepro? w ? ite timet 1 ? 4 ms note: t sys =1/f sys lvd & lvr electrical characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v lvr1 low voltage reset voltage lvr enable ? ?.1v option -5% ?.1 +5% v v lvr ? lvr enable ? ?.55v option ?.55 v lvr ? lvr enable ? ?.15v option ?.15 v lvr4 lvr enable ? ?.8v option ?.8 v lvd1 low voltage dete ?to? voltage lvden=1 ? v lvd =?.0v -5% ?.0 +5% v v lvd ? lvden=1 ? v lvd =?.?v ?.? v v lvd ? lvden=1 ? v lvd =?.4v ?.4 v v lvd4 lvden=1 ? v lvd =?.7v ?.7 v v lvd5 lvden=1 ? v lvd =?.0v ?.0 v v lvd6 lvden=1 ? v lvd =?.?v ?.? v v lvd7 lvden=1 ? v lvd =?.6v ?.6 v v lvd8 lvden=1 ? v lvd =4.0v 4.0 v v bg bandgap ?efe?en?e wit? buffe? voltage -?% 1.?5 +?% v i bg additional powe ? consumption if bandgap ?efe?en?e wit? buffe ? is used ?00 ?00 i lvr additional powe ? consumption if lvr is used ?v /?5glvdeoh:/?5hqdeoh 10 ?0 5v 15 ?0 i lvd additional powe ? consumption if lvd is used ?v /?'glvdeoh:/?'hqdeoh (lvr disable) 10 ?0 5v 15 ?0 ?v /?'glvdeoh:/?'hqdeoh (lvr enable) 1 ? 5v ? 4 t lvr low voltage widt ? to reset 1?0 ?40 480 v t lvd low voltage widt ? to inte??upt ?0 45 ?0 t lirc t lvds lvdo stable time )ru/?5hqdeoh/?'rii:rq 15 v )ru/?5glvdeoh/?'rii:rq 15 v t sreset softwa ? e reset widt ? to reset ?0 45 ?0 t lirc
rev. 1.00 ?0 ?a??? 1?? ?01? rev. 1.00 ?1 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom lcd d.c. characteristics ta= ?5c symbol parameter test condition min. typ. max. unit v dd condition i stb1 standby cu??ent (sleep) (f sys ? f wdt off ? f s =f sub =??768 o? ??k rc osc) ?v no load? system halt ? lcd on? wdt off ? c type? v lcd =v dd ? 1/? bias? ?.0 4.0 a 5v ?.0 5.0 a i stb? standby cu??ent (sleep) (f sys ? f wdt off ? f s =f sub =??768 o? ??k rc osc) ?v no load? system halt ? lcd on? wdt off ? c type? v lcd =v dd ? 1/? bias? ?.0 4.0 a 5v ?.0 5.0 a i stb? standby cu??ent (idle) (f sys ? f wdt off ? f s =f sub =??768 o? ??k rc osc) ?v no load? system halt ? lcd on? wdt off ? r type? v lcd =v dd ? 1/? bias (i bias =7.5a) 1?.5 ?0.0 a 5v ??.5 40.0 a i stb4 standby cu??ent (idle) (f sys ? f wdt off ? f s =f sub =??768 o? ??k rc osc) ?v no load? system halt ? lcd on? wdt off ? r type? v lcd =v dd ? 1/? bias (i bias =15a) ?1 40 a 5v ?5 60 a i stb5 standby cu??ent (idle) (f sys ? f wdt off ? f s =f sub =??768 o? ??k rc osc) ?v no load? system halt ? lcd on? wdt off ? r type? v lcd =v dd ? 1/? bias (i bias =45a) 51 80 a 5v 85 160 a i stb6 standby cu??ent (idle) (f sys ? f wdt off ? f s =f sub =??768 o? ??k rc osc) ?v no load? system halt ? lcd on? wdt off ? r type? v lcd =v dd ? 1/? bias (i bias =90a) ?6 160 a 5v 160 ??0 a i stb7 standby cu??ent (idle) (f sys ? f wdt off ? f s =f sub =??768 o? ??k rc osc) ?v no load? system halt ? lcd on? wdt off ? r type? v lcd =v dd ? 1/? bias (i bias =7.5a) 11 ?0 a 5v 18.? 40 a i stb8 standby cu??ent (idle) (f sys ? f wdt off ? f s =f sub =??768 o? ??k rc osc) ?v no load? system halt ? lcd on? wdt off ? r type? v lcd =v dd ? 1/? bias (i bias =15a) 16 ?5 a 5v ?6.6 50 a i stb? standby cu??ent (idle) (f sys ? f wdt off ? f s =f sub =??768 o? ??k rc osc) ?v no load? system halt ? lcd on? wdt off ? r type? v lcd =v dd ? 1/? bias (i bias =45a) ?6 50 a 5v 60 100 a i stb10 standby cu??ent (idle) (f sys ? f wdt off ? f s =f sub =??768 o? ??k rc osc) ?v no load? system halt ? lcd on? wdt off ? r type? v lcd =v dd ? 1/? bias (i bias =90a) 66 100 a 5v 110 ?00 a i ol? lcd common and segment sink cu??ent ?v v ol =0.1v lcd ?10 4?0 a 5v ?50 700 a i oh? lcd common and segment sou??e cu??ent ?v v oh =0.?v lcd -80 -160 a 5v -180 -?60 a
rev. 1.00 ?0 ?a??? 1?? ?01? rev. 1.00 ?1 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom power-on reset characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd sta? t voltage to ensu?e powe?-on reset 100 mv rr vdd v dd raising rate to ensu?e powe?-on reset 0.0?5 v/ms t por ? inimum time fo? v dd stays at v por to ensu?e powe?-on reset 1 ms system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o control system with maximum reliability and flexibility. this makes the device suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hxt, lxt, hirc, lirc, ec or erc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to frst obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
rev. 1.00 ?? ?a??? 1?? ?01? rev. 1.00 ?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom
? ? ? ? ? ? ? ? system clocking and pipelining
? ? ? ? ? ? ? ? ? ? instruction fetching program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non-consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. device program counter porgram counter high byte porgram counter low byte ht6?f?0a pc10~pc8 pcl7~pcl0 ht6?f40a pc11~pc8 ht6?f50a pc1?~pc8 program counter the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.00 ?? ?a??? 1?? ?01? rev. 1.00 ?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overfow. precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost.
device stack levels ht6?f?0a 4 ht6?f40a 8 ht6?f50a 8 arithmetic and logic unit C alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.00 ?4 ?a??? 1?? ?01? rev. 1.00 ?5 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom flash program memory the program memory is the location where the user code or program is stored. for this device series the program memory is flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. by using the appropriate programming tools, these flash devices offer users the fexibility to conveniently debug and develop their applications while also offering a means of feld programming and updating. structure the program memory has a capacity of up to 8k16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries information. table data, which can be setup in any location within the program memory, is addressed by separate table pointer registers. device capacity ht6?f?0a ?k16 ht6?f40a 4k16 ht6?f50a 8k16 0000h reset inte??upt ve?to? 0004h 001ch 07ffh 16 bits ht6?f?0a reset inte??upt ve?to? 16 bits ht6?f40a 0fffh reset inte??upt ve?to? 16 bits ht6?f50a 1fffh program memory structure
rev. 1.00 ?4 ?a??? 1?? ?01? rev. 1.00 ?5 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom special vectors within the program memory, certain locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. to use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register, tblp and tbhp. these registers defne the total address of the look-up table. after setting up the table pointer, the table data can be retrieved from the program memory using the tabrdc [m] or tabrdl [m] instructions, respectively. when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defned data memory register [m] as specifed in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data fow of the look-up table.

table program example the accompanying example shows how the table pointer and table data is defned and retrieved from the device. this example uses raw table data located in the last page which is stored there using the org statement. the value at this org statement is 700h which refers to the start address of the last page within the 2k program memory of the ht69f30a device. the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 706h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the tabrdc [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrdc [m] instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation.
rev. 1.00 ?6 ?a??? 1?? ?01? rev. 1.00 ?7 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise table pointer - note that this address ; is referenced to the last page or present page mov tblp, a : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempreg1 ; data at program memory address 706h transferred to ; to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at program memory address 705h transferred to ; tempreg2 and tblh ; in this example the data 1ah is transferred to ; tempreg1 and data 0fh to register tempreg2 ; the value 00h will be transferred to the high byte ; register tblh : : org 700h ; sets initial address of last page dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : in circuit programming C icp the provision of flash type program memory provides the user with a means of convenient and easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. holtek writer pins mcu programming pins pin description icpda pa0 p?og?amming se?ial data icpck pa ? p?og?amming clo?k vdd vdd powe? supply vss vss g?ound the program memory can be programmed serially in-circuit using this 4-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two additional lines are required for the power supply and one line for the reset. the technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature.
rev. 1.00 ?6 ?a??? 1?? ?01? rev. 1.00 ?7 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom during the programming process, taking control of the icpda and icpck pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins.
note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf. on-chip debug support C ocds there is an ev chip named ht69v0a which is used to emulate the ht69fx0a series of devices. the ht69v50a device also provides the on-chip debug function to debug the ht69fx0a series of devices during development process. the devices, ht69fx0a and ht69v50a, are almost functional compatible except the on-chip debug function and package types. users can use the ht69v50a device to emulate the ht69fx0a series of devices behaviors by connecting the ocdsda and ocdsck pins to the holtek ht-ide development tools. the ocdsda pin is the ocds data/address input/output pin while the ocdsck pin is the ocds clock input pin. when users use the ht69v50a ev chip for debugging, the corresponding pin functions shared with the ocdsda and ocdsck pins in the ht69fx0a series of devices will have no effect in the ht69v50a ev chip. however, the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp. for more detailed ocds information, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. holtek e-link pins ev chip pins pin description ocdsda ocdsda on-c?ip debug suppo?t data/add?ess input/output ocdsck ocdsck on-c?ip debug suppo?t clo?k input vdd vdd powe? supply gnd vss g?ound
rev. 1.00 ?8 ?a??? 1?? ?01? rev. 1.00 ?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom data memory the data memory is an 8-bit wide ram internal memory and is the location where temporary information is stored. divided into three sections, the frst of these is an area of ram where special function registers are located. these registers have fxed locations and are necessary for correct operation of the device. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. the third area is reserved for the lcd memory. this special area of data memory is mapped directly to the lcd display so data written into this memory area will directly affect the displayed data. switching between the different data memory banks is achieved by setting the bank pointer to the correct value. structure the data memory is subdivided into several banks, all of which are implemented in 8-bit wide ram. the data memory located in bank 0 is subdivided into two sections, the special purpose data memory and the general purpose data memory. the start address of the data memory for all devices is the address 00h. registers which are common to all microcontrollers, such as acc, pcl, etc., have the same data memory address. the lcd memory is mapped into bank 1. the banks 2 to 3 contain only general purpose data memory for those devices with larger data memory capacities. as the special purpose data memory registers are mapped into all bank areas, they can subsequently be accessed from any bank location. device capacity banks ht6?f?0a gene?al pu?pose: 1?88 lcd ?emo?y: ?5 0: 80h~ffh 1: 80h~?8h ht6?f40a gene?al pu?pose: ?568 lcd ?emo?y: ?7 0: 80h~ffh 1: 80h~a4h ?: 80h~ffh ht6?f50a gene?al pu?pose: ?848 lcd ?emo?y: 4? 0: 80h~ffh 1: 80h~b0h ?: 80h~ffh ?: 80h~ffh
rev. 1.00 ?8 ?a??? 1?? ?01? rev. 1.00 ?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom spe?ial pu?pose data ?emo?y gene?al pu?pose data ?emo?y 00h 7fh 80h ffh bank 0 bank ? bank ? bank 0 40h in bank 1 lcd ?emo?y in bank 1 data memory structure general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user programing for both reading and writing operations. by using the set [m].i and clr [m].i instructions individual bits can be set or reset under program control giving the user a large range of fexibility for bit manipulation in the data memory. special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant special function register section. note that for locations that are unused, any read instruction to these addresses will return the value 00h.
rev. 1.00 40 ?a??? 1?? ?01? rev. 1.00 41 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom 00h iar0 01h ?p0 0?h iar1 0?h ?p1 04h 05h acc 06h pcl 07h tblp 08h tblh 0?h tbhp 0ah status 0bh s?od 0ch lvdc 0dh integ 0eh wdtc 0fh tbc 10h intc0 11h intc1 1?h 1?h papu 18h pawu 1bh 1ah 1dh 1ch 1fh pa pac 1eh ht6?f?0a spe?ial pu?pose data ?emo?y bp 1?h 14h ?fi0 15h ?fi1 16h 17h ?fi? bank 0? 1 s?od1 lvrc unused pbpu pb pbc pcpu pc pcc pdpu pd pdc pepu pe pec pfpu pf pfc ?0h ?1h ??h ??h ?8h ?bh ?ah ?dh ?ch ?fh ?eh ??h ?4h ?5h ?6h ?7h ?0h ?1h ??h ??h ?8h ?bh ?ah ?dh ?ch ?fh ?eh ??h ?4h ?5h ?6h ?7h pafs pcfs pdfs pefs pffs sfs t?0c0 t?0c1 t?0dl t?0dh t?0al t?0ah 40h eec 41h eea 4?h eed 4?h 47h 48h 4?h 4ah 4bh 4ch 4dh 4eh lcdc 5fh bank 0 bank 1 t?1c0 t?1c 1 t?1dl t?1dh t?1al t?1ah 60h 61h 7fh unused : unused? ?ead as 00h unused unused unused unused unused unused unused unused unused unused unused ht69f30a special purpose data memory
rev. 1.00 40 ?a??? 1?? ?01? rev. 1.00 41 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom 00h iar0 01h ?p0 0?h iar1 0?h ?p1 04h 05h acc 06h pcl 07h tblp 08h tblh 0?h tbhp 0ah status 0bh s?od 0ch lvdc 0dh integ 0eh wdtc 0fh tbc 10h intc0 11h intc1 1?h 1?h papu 18h pawu 1bh 1ah 1dh 1ch 1fh pa pac 1eh ht6?f40a spe?ial pu?pose data ?emo?y bp 1?h 14h ?fi0 15h ?fi1 16h 17h ?fi? bank 0? 1? ? s?od1 lvrc unused pbpu pb pbc pcpu pc pcc pdpu pd pdc pepu pe pec pfpu pf pfc pgpu pg pgc ?0h ?1h ??h ??h ?8h ?bh ?ah ?dh ?ch ?fh ?eh ??h ?4h ?5h ?6h ?7h ?0h ?1h ??h ??h ?8h ?bh ?ah ?dh ?ch ?fh ?eh ??h ?4h ?5h ?6h ?7h pafs pbfs pcfs pdfs pefs pffs pgfs sfs t?0c0 t?0c1 t?0dl t?0dh t?0al t?0ah 40h eec 41h eea 4?h eed 4?h t??c0 47h t??c1 48h t?1c? 4?h t??dl 4ah t??dh 4bh t??al 4ch t??ah 4dh t?1bl 4eh t?1bh 4fh 50h 51h 5?h lcdc 5fh 5?h 54h 55h 56h 57h bank 0? ? bank 1 t?1c0 t?1c1 t?1dl t?1dh t?1al t?1ah 60h 61h 7fh unused : unused? ?ead as 00h unused unused unused unused unused unused ht69f40a special purpose data memory
rev. 1.00 4? ?a??? 1?? ?01? rev. 1.00 4? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom 00h iar0 01h ?p0 0?h iar1 0?h ?p1 04h 05h acc 06h pcl 07h tblp 08h tblh 0?h tbhp 0ah status 0bh s?od 0ch lvdc 0dh integ 0eh wdtc 0fh tbc 10h intc0 11h intc1 1?h 1?h papu 18h pawu 1bh 1ah 1dh 1ch 1fh pa pac 1eh ht6?f40a spe?ial pu?pose data ?emo?y bp 1?h 14h ?fi0 15h ?fi1 16h 17h ?fi? bank 0? 1? ?? ? s?od1 lvrc unused pbpu pb pbc pcpu pc pcc pdpu pd pdc pepu pe pec pfpu pf pfc pgpu pg pgc phpu ph phc ?0h ?1h ??h ??h ?8h ?bh ?ah ?dh ?ch ?fh ?eh ??h ?4h ?5h ?6h ?7h ?0h ?1h ??h ??h ?8h ?bh ?ah ?dh ?ch ?fh ?eh ??h ?4h ?5h ?6h ?7h pafs pbfs pcfs pdfs pefs pffs pgfs phfs sfs t?0c0 t?0c1 t?0dl t?0dh t?0al t?0ah 40h eec 41h eea 4?h eed 4?h t??c0 47h t??c1 48h t?1c? 4?h t??dl 4ah t??dh 4bh t??al 4ch t??ah 4dh t?1bl 4eh t?1bh 4fh 50h 51h 5?h lcdc 58h 5fh 5?h 54h 55h 56h 57h bank 0? ?? ? bank 1 t?1c0 t?1c1 t?1dl t?1dh t?1al t?1ah t??rp 60h 61h 7fh unused : unused? ?ead as 00h unused unused HT69F50A special purpose data memory
rev. 1.00 4? ?a??? 1?? ?01? rev. 1.00 4? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom special function register description most of the special function register details will be described in the relevant functional section; however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specifed by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according to bp register. direct addressing can only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. indirect addressing program example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with frst ram address mov mp0,a ; setup memory pointer with frst ram address loop: clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specifc ram addresses.
rev. 1.00 44 ?a??? 1?? ?01? rev. 1.00 45 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom bank pointer C bp depending upon which device is used, the data memory is divided into several banks. selecting the required data memory area is achieved using the bank pointer. bits 0~1 of the bank pointer are used to select data memory banks 0~3. the data memory is initialised to bank 0 after a reset, except for a wdt time-out reset in the power down mode, in which case, the data memory bank remains unaffected. it should be noted that the special function data memory is not affected by the bank selection, which means that the special function registers can be accessed from within any bank. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. accessing data from banks other than bank 0 must be implemented using indirect addressing. as both the program memory and data memory share the same bank pointer register, care must be taken during programming. device bit 7 6 5 4 3 2 1 0 ht6?f?0a d?bp0 ht6?f40a d?bp1 d?bp0 ht6?f50a d?bp1 d?bp0 bp register list bp register ? ht69f30a bit 7 6 5 4 3 2 1 0 name d?bp0 r/w r/w por 0 bit 7~1 unimplemented, read as "0" bit 0 dmbp0: data memory bank point 0: bank 0 1: bank 1 ? ht69f40a bit 7 6 5 4 3 2 1 0 name d?bp1 d?bp0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 dmbp1, dmbp0: data memory bank point 00: bank 0 01: bank 1 10: bank 2 11: undefned
rev. 1.00 44 ?a??? 1?? ?01? rev. 1.00 45 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ? HT69F50A bit 7 6 5 4 3 2 1 0 name d?bp1 d?bp0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 dmbp1, dmbp0: data memory bank point 00: bank 0 01: bank 1 10: bank 2 11: bank 3 accumulator C acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to control operation of the look-up table which is stored in the program memory. tblp and tbhp are the table pointer and indicates the location where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location.
rev. 1.00 46 ?a??? 1?? ?01? rev. 1.00 47 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (to). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exception of the to and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf fag. in addition, operations related to the status register may give different results due to the different instruction operations. the to fag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt instruction. the pdf fag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
rev. 1.00 46 ?a??? 1?? ?01? rev. 1.00 47 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 x x x x x unknown bit 7, 6 unimplemented, read as 0 bit 5 to: watchdog time-out fag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred bit 4 pdf: power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov: overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa bit 2 z: zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac: auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c: carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.00 48 ?a??? 1?? ?01? rev. 1.00 4? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom eeprom data memory the eeprom data memory capacity is up to 1288 bits for this series of devices. unlike the program memory and ram data memory, the eeprom data memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. read andwrite operations to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. device capacity address ht6?f?0a 648 00h~?fh ht6?f40a 1?88 00h~7fh ht6?f50a 1?88 00h~7fh eeprom registers three registers control the overall operation of the internal eeprom data memory. these are the address register, eea, the data register, eed and a single control register, eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same was as any other special function register. the eec register however, being located in bank1, cannot be addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register, iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register, bp, set to the value, 01h, before any operations on the eec register are executed. eeprom register list ? ht69f30a register name bit 7 6 5 4 3 2 1 0 eea eea5 eea4 eea? eea? eea1 eea0 eed eed7 eed6 eed5 eed4 eed? eed? eed1 eed0 eec wren wr rden rd ? ht69f40a/HT69F50A register name bit 7 6 5 4 3 2 1 0 eea eea6 eea5 eea4 eea? eea? eea1 eea0 eed eed7 eed6 eed5 eed4 eed? eed? eed1 eed0 eec wren wr rden rd eea register ? ht69f30a bit 7 6 5 4 3 2 1 0 name eea5 eea4 eea? eea? eea1 eea0 r/w r/w r/w r/w r/w r/w r/w por x x x x x x x: unknown bit 7~6 unimplemented, read as "0" bit 5~0 eea5~eea0: data eeprom address bit 5~bit 0
rev. 1.00 48 ?a??? 1?? ?01? rev. 1.00 4? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ? ht69f40a/HT69F50A bit 7 6 5 4 3 2 1 0 name eea6 eea5 eea4 eea? eea? eea1 eea0 r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x: unknown bit 7 unimplemented, read as "0" bit 6~0 eea6~eea0: data eeprom address bit 6~bit 0 eed register bit 7 6 5 4 3 2 1 0 name eed5 eed4 eed5 eed4 eed? eed? eed1 eed0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x: unknown bit 7~0 eed7~eed0: data eeprom data bit 7~bit 0 eec register bit 7 6 5 4 3 2 1 0 name wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3 wren: data eeprom write operation enable 0: disable 1: enable this is the data eeprom write operation enable bit which must be set high before datat eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr: data eeprom write control 0: write cycle has fnished 1: activate a write cycle this is the data eeprom write control bit and when set high by the application program will activate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no effect if the wren bit has not frst been set high. bit 1 rden: data eeprom read operation enable 0: disable 1: enable this is the data eeprom read operation enable bit which must be set high before datat eeprom read operations are carried out. clearing this bit to zero will inhibit data eeprom read operations. bit 0 rd: data eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the application program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no effect if the rden bit has not frst been set high. note: the wren, wr, rden and rd bits can not be set to 1 at the same time in one instruction. the wr and rd bits can not be set to 1 at the same time.
rev. 1.00 50 ?a??? 1?? ?01? rev. 1.00 51 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom reading data from the eeprom to read data from the eeprom, the read enable bit, rden, in the eec register must frst be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eearegister. if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle terminates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register. the data will remain in the eed register until another read or write operation is executed. the application program can poll the rd bit to determine when the data is valid for reading. writing data to the eeprom the eeprom address of the data to be written must frst be placed in the eea register and the data placed in the eed register. to write data to the eeprom, the write enable bit, wren, in the eec register must frst be set high to enable the write function. after this, the wr bit in the eec register must be immediately set high to initiate a write cycle. these two instructions must be executed consecutively. the global interrupt bit emi should also frst be cleared before implementing any write operations, and then set again after the write cycle has started. note that setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on the write enable bit in the control register will be cleared preventing any write operations. also at power-on the bank pointer, bp, will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the write enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must frst be enabled by setting the dee bit in the relevant interrupt register. however as the eeprom is contained within a multi-function interrupt, the associated multi- function interrupt enable bit must also be set. when an eeprom write cycle ends, the def request fag and its associated multi-function interrupt request fag will both be set. if the global, eeprom and multi-function interrupts are enabled and the stack is not full, a jump to the associated multi-function interrupt vector will take place. when the interrupt is serviced only the multi-function interrupt fag will be automatically reset, the eeprom interrupt fag must be manually reset by the application program. more details can be obtained in the interrupt section.
rev. 1.00 50 ?a??? 1?? ?01? rev. 1.00 51 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensuring that the write enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly. the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. programming examples reading data from the eeprom C polling mothod mov a, eeprom_adres ; user defned address mov eea, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a set iar1.1 ; set rden bit, enable read operations set iar1.0 ; start read cycle - set rd bit back: sz iar1.0 ; check for read cycle end jmp back clr iar1 ; disable eeprom read/write clr bp mov a, eed ; move read data to register mov read_data, a writing data to the eeprom C polling mothod clr emi mov a, eeprom_adres ; user defned address mov eea, a mov a, eeprom_data ; user defned data mov eed, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a set iar1.3 ; set wren bit, enable write operations set iar1.2 ; start write cycle - set wr bit - executed immediately ; after set wren bit set emi back: sz iar1.2 ; check for write cycle end jmp back clr iar1 ; disable eeprom read/write clr bp
rev. 1.00 5? ?a??? 1?? ?01? rev. 1.00 5? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom oscillator various oscillator options offer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and registers. oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for the watchdog timer and time base interrupts. external oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. all oscillator options are selected through the configuration options. the higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. with the capability of dynamically switching between fast and slow system clock, the device has the fexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. pins exte?nal c?ystal hxt 400khz~16?hz osc1/osc? exte?nal rc erc 8?hz osc1 exte?nal clo?k ec 400khz~?0?hz osc1 inte?nal hig? speed rc hirc 4? 8 o? 1??hz exte?nal low speed c?ystal lxt ??.768khz xt1/xt? inte?nal low speed rc lirc ??khz oscillator types system clock confgurations there are fve methods of generating the system clock, three high speed oscillators and two low speed oscillators. the high speed oscillators are is the external crystal/ceramic oscillator, external rc network oscillator and the internal 4mhz, 8mhz or 12mhz rc oscillator. the two low speed oscillators are the internal 32khz rc oscillator and the external 32.768khz crystal oscillator. selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2~cks0 bits in the smod register and as the system clock can be dynamically selected.
rev. 1.00 5? ?a??? 1?? ?01? rev. 1.00 5? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom hxt hirc p?es?ale? f h lirc lxt hig? speed os?illation (hosc) low speed os?illation (losc) f h /? f h /16 f h /64 f h /8 f h /4 f h /?? hig? speed os?illation configu?ation option low speed os?illation configu?ation option cks[?:0]? hlclk f sys fast wake-up f?om sleep ?ode o? idle ?ode cont?ol (fo? hxt only) 8 lcd d?ive? f sys /4 f sub f tb wdt time base tbck fs erc ec external crystal/ceramic oscillator C hxt the external crystal/ceramic system oscillator is one of the high frequency oscillator choices, which is selected via configuration option. for most crystal oscillator configurations, the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. however, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur. the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer's specifcation. an additional confguration option must be setup to confgure the device according to whether the oscillator frequency is high, defned as equal to or above 1mhz, or low, which is defned as below 1mhz.
? ? ?? crystal/resonator oscillator C hxt
rev. 1.00 54 ?a??? 1?? ?01? rev. 1.00 55 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom crystal oscillator c1 and c2 values crystal frequency c1 c2 1??hz 0pf 0pf 8?hz 0pf 0pf 4?hz 0pf 0pf 1?hz 100pf 100pf 455khz (see note?) 100pf 100pf note: 1. c1 and c? values a?e fo? guidan? e only. 2. xtal mode confguration option: 455khz. crystal recommended capacitor values external rc oscillator C erc using the erc oscillator only requires that a resistor, with a value between 56k and 2.4m, is connected between osc1 and vdd, and a capacitor is connected between osc1 and ground, providing a low cost oscillator configuration. it is only the external resistor that determines the oscillation frequency; the external capacitor has no infuence over the frequency and is connected for stability purposes only. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a resistance/frequency reference point, it can be noted that with an external 150k resistor connected and with a 5v voltage power supply and temperature of 25c degrees, the oscillator will have a frequency of 4mhz within a tolerance of 2%. here only the osc1 pin is used, which is shared with i/o pin pb0, leaving pin pb1 free for use as a normal i/o pin. external rc oscillator erc internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has three fxed frequencies of either 4mhz, 8mhz or 12mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of either 3v or 5v and at a temperature of 25c degrees, the fxed oscillation frequency of 4mhz, 8mhz or 12mhz will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pb0 and pb1 are free for use as normal i/o pins.
rev. 1.00 54 ?a??? 1?? ?01? rev. 1.00 55 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom external 32.768khz crystal oscillator C lxt the external 32.768khz crystal system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. this clock source has a fxed frequency of 32.768khz and requires a 32.768khz crystal to be connected between pins xt1 and xt2. the external resistor and capacitor components connected to the 32.768khz crystal are necessary to provide oscillation. for applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. during power-up there is a time delay associated with the lxt oscillator waiting for it to start-up. when the microcontroller enters the sleep or idle mode, the system clock is switched off to stop microcontroller activity and to conserve power. however, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. to do this, another clock, independent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer's specification. the external parallel feedback resistor, rp, is required. some confguration options determine if the xt1/xt2 pins are used for the lxt oscillator or as i/o pins. ? if the lxt oscillator is not used for any clock source, the xt1/xt2 pins can be used as normal i/o pins. ? if the lxt oscillator is used for any clock source, the 32.768khz crystal should be connected to the xt1/xt2 pins.
? ? ? ?? ?- ? ? ? external lxt oscillator lxt oscillator c1 and c2 values crystal frequency c1 c2 ??.768khz 10pf 10pf note:1. c1 a nd c? values a?e fo? guidan? e only. ?. r p =5? ~10m is recommended. 32.768khz crystal recommended capacitor values
rev. 1.00 56 ?a??? 1?? ?01? rev. 1.00 57 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the tbc register. lxtlp bit lxt mode 0 qui?k sta?t 1 low-powe? after power on the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly. however, after the lxt oscillator has fully powered up it can be placed into the low-power mode by setting the lxtlp bit high. the oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power-on. it should be noted that, no matter what condition the lxtlp bit is set to, the lxt oscillator will always function normally, the only difference is that it will take more time to start up if in the low-power mode. internal 32khz oscillator C lirc the internal 32khz system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. it is a fully integrated rc oscillator with a typical frequency of 32khz at 5v, requiring no external components for its implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25 c degrees, the fxed oscillation frequency of 32khz will have a tolerance within 10%. external clock C ec the system clock can also be supplied by an externally supplied clock giving users a method of synchronizing their external hardware to the microcontroller operation. this is selected using a configuration option and supplying the clock on pin osc1. pin osc2 should be left floating if the external oscillator is used. the internal oscillator circuit contains a filter circuit to reduce the possibility of erratic operation due to noise on the oscillator pin, however as the flter circuit consumes a certain amount of power, a oscillator confguration option exists to turn this flter off. not using the internal filter should be considered in power sensitive applications and where the externally supplied clock is of a high integrity and supplied by a low impedance source. supplementary oscillators the low speed oscillators, in addition to providing a system clock source are also used to provide a clock source to two other device functions. these are the watchdog timer, the lcd driver and the time base interrupts.
rev. 1.00 56 ?a??? 1?? ?01? rev. 1.00 57 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom operating modes and system clocks present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conficting requirements that are especially true in battery powered portable applications. the fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. as holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clock the device has many different clock sources for both the cpu and peripheral function operation. by providing the user with a wide range of clock options using confguration options and register programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency, f h , or low frequency, f sub , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register. the high speed system clock can be sourced from an hxt, erc or hirc oscillator, selected via a confguration option. the low speed system clock source can be sourced from the clock, f sub . if f sub is selected then it can be sourced by either the lxt or lirc oscillators, selected via a confguration option. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. the f sub clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. hxt hirc p?es?ale? f h lirc lxt hig? speed os?illation (hosc) low speed os?illation (losc) f h /? f h /16 f h /64 f h /8 f h /4 f h /?? hig? speed os?illation configu?ation option low speed os?illation configu?ation option cks[?:0]? hlclk f sys fast wake-up f?om sleep ?ode o? idle ?ode cont?ol (fo? hxt only) 8 lcd d?ive? f sys /4 f sub f tb wdt time base tbck fs erc ec system clock confgurations note: when the system clock source f sys is switched to f sub from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use.
rev. 1.00 58 ?a??? 1?? ?01? rev. 1.00 5? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom system operation modes there are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. there are two modes allowing normal operation of the microcontroller, the normal mode and slow mode. the remaining four modes, the sleep0, sleep1, idle0 and idle1 mode are used when the microcontroller cpu is switched off to conserve power. operating mode description cpu f sys f sub f s nor? al ?ode on f h ~f h /64 on on slow ?ode on f sub on on idle0 ?ode off off on on idle1 ?ode off on on on sleep0 ?ode off off off off sleep1 ?ode off off on on normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the hxt, erc, ec or hirc oscillators. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register. although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally although now with a slower speed clock source. the clock source used will be from one of the low speed oscillators, either the lxt or the lirc. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep0 mode the sleep mode is entered when an halt instruction is executed and when the idlen bit in the smod register is low. in the sleep0 mode the cpu will be stopped, and the f sub and f s clocks will be stopped too, and the watchdog timer function is disabled. in this mode, the lvden is must set to "0". if the lvden is set to "1", it won't enter t he sleep0 mode. sleep1 mode the sleep1 mode is entered when an halt instruction is executed and when the idlen bit in the smod register is low. in the sleep1 mode the cpu will be stopped. however the f s will continue to operate if the lvden is 1 or the watchdog timer function is enabled as its clock source is from the f sub . idle0 mode the idle0 mode is entered when a halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the smod1 register is low. in the idle0 mode the system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the watchdog timer, tms and lcd driver. in the idle0 mode, the system oscillator will be stopped while the watchdog timer clock, f s , will be on.
rev. 1.00 58 ?a??? 1?? ?01? rev. 1.00 5? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom idle1 mode the idle1 mode is entered when an halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the smod1 register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the watchdog timer, tms and sim. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. in the idle1 mode the watchdog timer clock, f s , will also be on. control register a register pair, smod and smod1, is used for overall control of the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 name cks? cks1 cks0 fsten lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 1 1 bit 7~5 cks2~cks0: the system clock selection when hlclk is "0" 000: f sub (f lxt or f lirc ) 001: f sub (f lxt or f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source the lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 fsten: fast wake-up control (only for hxt) 0: disable 1: enable this is the fast wake-up control bit which determines if the f sub clock source is initially used after the device wakes up. when the bit is high, the f sub clock source can be used as a temporary system clock to provide a faster wake up time as the f sub clock is available. bit 3 lto: low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscillator ready fag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode but after a wake-up has occurred, the fag will change to a high level after 1~2 clock cycles if the lirc oscillator is used.
rev. 1.00 60 ?a??? 1?? ?01? rev. 1.00 61 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom bit 2 hto: high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready fag which indicates when the high speed system oscillator is stable. this fag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as 1 by the application program after device power-on. the fag will be low when in the sleep or idle0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the hxt oscillator is used. bit 1 idlen: idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the halt instruction is executed. if this bit is high, when a halt instruction is executed the device will enter the idle mode. in the idle1 mode the cpu will stop running but the system clock will continue to keep the peripheral functions operational, if fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a halt instruction is executed. bit 0 hlclk: system clock selection 0: f h /2~f h /64 or f sub 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f sub clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2~f h /64 or f sub clock will be selected. when system clock switches from the f h clock to the f sub clock and the f h clock will be automatically switched off to conserve power. smod1 register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 "x" unknown bit 7 fsyson: f sys control in idle mode 0: disable 1: enable bit 6~3 unimplemented, read as "0" bit 2 lvrf: lvr function reset fag 0: not occurred 1: occurred this bit is set to 1 when a specifc low voltage reset situation occurs. this bit can only be cleared to 0 by the application program. bit 1 lrf: lvr control register software reset fag 0: not occurred 1: occurred this bit is set to 1 if the lvrc register contains any non defned lvr voltage register values. this in effect acts like a software-reset function. this bit can only be cleared to 0 by the application program. bit 0 wrf: wdt control register software reset fag 0: not occurred 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to 0 by the application program.
rev. 1.00 60 ?a??? 1?? ?01? rev. 1.00 61 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom fast wake-up to minimise power consumption the device can enter the sleep or idle0 mode, where the system clock source to the device will be stopped. however when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilize and allow normal operation to resume. to ensure the device is up and running as fast as possible a fast wake-up function is provided, which allows f sub , namely the lirc oscillator, to act as a temporary clock to frst drive the system until the original system oscillator has stabilised. as the clock source for the fast wake-up function is f sub , the fast wake-up function is only available in the sleep1 and idle0 modes. when the device is woken up from the sleep0 mode, the fastwake-up function has no effect because the f sub clock is stopped. the fastwake-up enable/disable function is controlled using the fsten bit in the smod register. if the hxt oscillator is selected as the normal mode system clock and if the fast wake-up function is enabled, then it will take one to two t sub clock cycles of the lirc oscillator for the system to wake-up. the system will then initially run under the f sub clock source until 1024 hxt clock cycles have elapsed, at which point the hto fag will switch high and the system will switch over to operating from the hxt oscillator. if the erc/hirc or ec/lirc oscillator is used as the system oscillator, then it will take15~16 clock cycles of the erc/hirc oscillator or 1~2 clock cycles of the lirc osrillator respectively to wake up the system from the sleep or idle0 mode. the fast wake-up bit, fsten will have no effect in these cases. system oscillator fsten bit wake-up time (sleep0 mode) wake-up time (sleep1 mode) wake-up time (idle0 mode) wake-up time (idle1 mode) hxt 0 10? 4 hxt ?y?les 10? 4 hxt ?y?les 1~? hxt ?y?les 1 10? 4 hxt ?y?les 1~? f sub ?y?les (system ?uns wit? f sub frst for 1024 hxt ?y?les and t?en swit??es ove? to ?un wit? t? e hxt ?lo?k ) 1~? hxt ?y?les erc x 15~16 erc ?y?les 15~16 erc ?y?les 1~? erc ?y?les hirc x 15~16 hirc ?y?les 15~16 hirc ?y?les 1~? hirc ?y?les ec x 1~? ec ?y?les 1~? ec ?y?les 1~? ec ?y?les lirc x 1~? lirc ?y?les 1~? lirc ?y?les 1~? lirc ?y?les lxt x 10? 4 lxt ?y?les 10? 4 lxt ?y?les 1~? lxt ?y?les wake-up times note that if the watchdog timer is disabled, which means that the f sub clock drived from the lxt or lirc oscillator is off, then there will be no fast wake-up function available when the device wakes-up from the sleep0 mode. operating mode switching the device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. in this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the halt instruction. when a halt instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the smod1 register.
rev. 1.00 6? ?a??? 1?? ?01? rev. 1.00 6? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f sub . if the clock is from the f sub , the high speed clock source will stop running to conserve power. when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the tms and the lcd driver. the accompanying fowchart shows what happens when the device moves between the various operating modes.

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? operating mode switching and wake-up the device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. in this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the halt instruction. when a halt instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the wdtc register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f l . if the clock is from the f l , the high speed clock source will stop running to conserve power. when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the tms and the sim. the accompanying fowchart shows what happens when the device moves between the various operating modes.
rev. 1.00 6? ?a??? 1?? ?01? rev. 1.00 6? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom normal mode to slow mode switching when running in the normal mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to "0" and set the cks2~cks0 bits to "000" or "001" in the smod register. this will then use the low speed system oscillator which will consume less power. users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lxt or the lirc oscillators and therefore requires these oscillators to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register.
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rev. 1.00 64 ?a??? 1?? ?01? rev. 1.00 65 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom
? ? ? ? ? ? ?? ?? ? - ?? ? ? ? ? ?? ?? ? - ?? ? ? ? ? ? ?? ?? ? - ? ?? ? ? ? ? ?? ?? ? - ?? ? slow mode to normal mode switching in slow mode the system uses eit her the lxt or lirc low speed system oscillator. to switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to "1" or hlclk bit is "0", but cks2~cks0 is set to "010", "011", "100", "101", "110" or "111". as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used.
rev. 1.00 64 ?a??? 1?? ?01? rev. 1.00 65 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom entering the sleep0 mode there is only one way for the device to enter the sleep0 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 0 and the wdt and lvd both off. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and the f sub clock will be stopped and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped as the wdt is disabled. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the sleep1 mode there is only one way for the device to enter the sleep1 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 0 and the wdt or lvd on. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the halt instruction, but the wdt or lvd will remain with the clock source coming from the f sub clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting as the wdt is enabled and its clock source is selected to come from the f sub clock. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in smod1 register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the halt instruction, but the f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting as the wdt clock source is derived from the f sub clock. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared.
rev. 1.00 66 ?a??? 1?? ?01? rev. 1.00 67 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in smod1 register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and f sub clock will be on and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting as the wdt clock source is derived from the f sub clock. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have different package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the lxt or lirc oscillator. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps.
rev. 1.00 66 ?a??? 1?? ?01? rev. 1.00 67 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external reset ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a wdt overfow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the "halt" instruction. the to fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the pawu register to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up occurs, the program will resume execution at the instruction following the "halt" instruction. if the system is woken up by an interrupt, then two possible situations may occur. the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "halt" instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled. programming considerations the hxt and lxt oscillators both use the same sst counter. for example, if the system is woken up from the sleep0 mode and both the hxt and lxt oscillators need to start-up from an off state. the lxt oscillator uses the sst counter after hxt oscillator has fnished its sst period. ? if the device is woken up from the sleep0 mode to the normal mode, the high speed system oscillator needs an sst period. the device will execute first instruction after hto is "1". at this time, the lxt oscillator may not be stable if f sub is from lxt oscillator. the same situation occurs in the power-on state. the lxt oscillator is not ready yet when the frst instruction is executed. ? if the device is woken up from the sleep1 mode to normal mode, and the system clock source is from hxt oscillator and fsten is 1, the system clock can be switched to the lxt or lirc oscillator after wake up. ? there are peripheral functions, such as wdt, tms and lcd driver, for which the f sys is used. if the system clock source is switched from f h to f sub , the clock source to the peripheral functions mentioned above will change accordingly. ? the on/off condition of f sub and f s depends upon whether the wdt is enabled or disabled as the wdt clock source is selected from f sub .
rev. 1.00 68 ?a??? 1?? ?01? rev. 1.00 6? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the watchdog timer clock source is provided by the internal clock f s , which is in turn supplied by the f sub clock. the f sub clock can be sourced from either the lxt or lirc oscillator selected by a confguration option. the lirc internal oscillator has an approximate frequency of 32khz and this specified internal clock period can vary with v dd , temperature and process variations. the lxt oscillator is supplied by an external 32.768khz crystal. the watchdog timer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. watchdog timer control register a single register, wdtc, controls the required time-out period as well as the enable/disable operation. this register controls the overall operation of the watchdog timer. wdtc register bit 7 6 5 4 3 2 1 0 name we4 we? we? we1 we0 ws? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 we4~we0: wdt function enable control if the wdt confguration option is always enable: 10101 or 01010: enabled other values: reset mcu if the wdt confguration option is application program enable: 10101: disabled 01010: enabled other values: reset mcu if these bits are changed due to adverse environmental conditions, the microcontroller will be reset. the reset operation will be activated after 2~3 lirc clock cycles and the wrf bit in the ctrl register will be set to 1. bit 2~0 ws2~ws0: select wdt timeout period 000: 2 8 /f s 001: 2 10 /f s 010: 2 12 /f s 011: 2 14 /f s 100: 2 15 /f s 101: 2 16 /f s 110: 2 17 /f s 111: 2 18 /f s these three bits determine the division ratio of the watchdog timer source clock, which in turn determines the timeout period.
rev. 1.00 68 ?a??? 1?? ?01? rev. 1.00 6? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom smod1 register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 x unknown bit 7 fsyson: f sys control in idle mode described elsewhere. bit 6~3 unimplemented, read as "0" bit 2 lvrf: lvr function reset fag described elsewhere. bit 1 lrf: lvr control register software reset fag described elsewhere. bit 0 wrf: wdt control register software reset fag 0: not occurred 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to 0 by the application program. watchdog timer operation the watchdog timer operates by providing a device reset when its timer overfows. this means that in the application program and during normal operation the user has to strategically clear the watchdog timer before it overfows to prevent the watchdog timer from executing a reset. this is done using the clear watchdog instructions. if the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the watchdog timer will overfow and reset the device. the watchdog timer function is determined using a confguration option. with regard to the watchdog timer enable/disable function, there are also fve bits, we4~we0, in the wdtc register to offer the additional enable/disable control and reset control of the watchdog timer. if the wdt function confguration option is determined that the wdt function is always enabled, the we4~we0 bits still have effects on the wdt function. when the we4~we0 bits value is equal to 01010b or 10101b, the wdt function is enabled. however, if the we4~we0 bits are changed to any other values except 01010b and 10101b, which is caused by the environmental noise, it will reset the microcontroller after 2~3 f sub clock cycles. if the wdt function confguration option is determined that the wdt function is controlled by the wdtc control register using the application program, the we4~we0 values can determine which mode the wdt operates in. the wdt function will be disabled when the we4~we0 bits are set to a value of 10101b while the wdt function will be enabled if the we4~we0 bits are equal to 01010b. if the we4~we0 bits are set to any other values, other than 01010b and 10101b, it will reset the device after 2~3 f sub clock cycles. after power on these bits will have a value of 01010b. wdt function control we4~we0 bits wdt function appli?ation p?og?am enabled 10101b disable 01010b enable any ot?e? value reset ?cu always enabled 01010b o? 10101b enable any ot?e? value reset ?cu watchdog timer enable/disable control
rev. 1.00 70 ?a??? 1?? ?01? rev. 1.00 71 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the sleep or idle mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the watchdog timer. the frst is a wdt reset, which means a certain value except 01010b and 10101b written into the we4~we0 feld, the second is using the watchdog timer software clear instruction and the third is via a halt instruction. there is only one method of using software instruction to clear the watchdog timer. that is to use the single clr wdt instruction to clear the wdt contents. the maximum time out period is when the 2 18 division ratio is selected. as an example, with a 32khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration. clr wdtinst?u?tion 8-stage divide? wdt p?es?ale? we4~we0 bits wdtc registe? reset ?cu lxt f s f sub f s /? 8 8-to-1 ?ux clr ws?~ws0 (f s /? 8 ~ f s /? 18 ) wdt time-out (? 8 /f s ~ ? 18 /f s ) lirc ? u x low speed os?illato? configu?ation option watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the frst program instruction. after this power-on reset, certain important internal registers will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the is running. one example of this is where after power has been applied and the is already running, the res line is forcefully pulled low. in such a case, known as a normal operation reset, some of the registers remain unchanged allowing the to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the . all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is implemented in situations where the power supply voltage falls below a certain threshold.
rev. 1.00 70 ?a??? 1?? ?01? rev. 1.00 71 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom reset functions there are five ways in which a reset can occur, through events occurring both internally and externally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is frst applied to the. as well as ensuring that the program memory begins execution from the frst memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. power-on reset timing chart note: t rstd is power-on delay, typical time=50ms res pin as the reset pin is shared with an i/o pin, the reset function must be selected using a confguration option. although the has an internal rc reset function, if the v dd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the will begin normal operation. the abbreviation sst in the fgures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected between v ss and the res pin will provide a suitable external reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset circuit shown is recommended. external res circuit note: * it is recommended that this component is added for added esd protection. ** it is recommended that this component is added in environments where power line noise is signifcant.
rev. 1.00 7? ?a??? 1?? ?01? rev. 1.00 7? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom more information regarding external reset circuits is located in application note ha0075e on the holtek website. pulling the res pin low using external hardware will also execute a device reset. in this case, as in the case of other resets, the program counter will reset to zero and program execution initiated from this point. res reset timing chart note: t rstd is power-on delay, typical time=16.7ms low voltage reset C lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. the lvr function is always enabled with a specifc lvr voltage, v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally and the lvrf bit in the smod1 register will also be set to 1. for a valid lvr signal, a low supply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that specifed by t lvr in the a.c. characteristics. if the low supply voltage state does not exceed this value, the lvr will ignore the low supply voltage and will not perform a reset function. the actual v lvr value can be selected by the lvs bits in the lvrc register. if the lvs7~lvs0 bits have any other value, which may perhaps occur due to adverse environmental conditions such as noise, the lvr will reset the device after 2~3 f sub clock cycles. when this happens, the lrf bit in the smod1 register will be set to 1. after power on the register will have the value of 01010101b. note that the lvr function will be automatically disabled when the device enters the power down mode. note: t rstd is power-on delay, typical time=50ms low voltage reset timing chart
rev. 1.00 7? ?a??? 1?? ?01? rev. 1.00 7? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ? lvrc register bit 7 6 5 4 3 2 1 0 name lvs7 lvs6 lvs5 lvs4 lvs ? lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~0 lvs7~lvs0: lvr voltage select 01010101: 2.1v 00110011: 2.55v 10011001: 3.15v 10101010: 3.8v any other values: generates mcu reset C register is reset to por value when an actual low voltage condition occurs, as specifed by one of the four defned lvr voltage values above, an mcu reset will be generated. the reset operation will be activated after 2~3 f sub clock cycles. in this situation the register contents will remain the same after such a reset occurs. any register value, other than the four defned register values above, will also result in the generation of an mcu reset. the reset operation will be activated after 2~3 f sub clock cycles. however in this situation the register contents will be reset to the por value. ? smod1 register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 "x" unknown bit 7 fsyson: f sys control in idle mode described elsewhere. bit 6~3 unimplemented, read as "0" bit 2 lvrf: lvr function reset fag 0: not occurred 1: occurred this bit is set to 1 when a specifc low voltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 lrf: lvr control register software reset fag 0: not occurred 1: occurred this bit is set to 1 if the lvrc register contains any non defned lvr voltage register values. this in effect acts like a software-reset function. this bit can only be cleared to 0 by the application program. bit 0 wrf: wdt control register software reset fag described elsewhere. watchdog time-out reset during normal operation the watchdog time-out reset during normal operation is the same as a hardware res pin reset except that the watchdog time-out fag to will be set to "1". wdt time-out reset during normal operation timing chart note: t rstd is power-on delay, typical time=16.7ms
rev. 1.00 74 ?a??? 1?? ?01? rev. 1.00 75 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom watchdog time-out reset during sleep or idle mode the watchdog time-out reset during sleep or idle mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to "0" and the to fag will be set to "1". refer to the a.c. characteristics for t sst details. wdt time-out reset during sleep or idle timing chart note: the t sst is 15~16 clock cycles if the system clock source is provided by erc or hirc. the t sst is 1024 clock for hxt or lxt. the t sst is 1~2 clock for lirc. reset initial conditions the different types of reset described affect the reset fags in different ways. these fags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the sleep or idle mode function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 powe?-on ?eset u u res o? lvr ?eset du? ing nor? al o? slow ?ode ope?ation 1 u wdt time-out ?eset du?ing nor? al o? slow ?ode ope?ation 1 1 wdt time-out ?eset du?ing idle o? sleep ?ode ope?ation "u" stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p?og?am counte? reset to ze?o inte??upts all inte??upts will be disabled wdt ? time base clea? afte? ?eset? wdt begins ?ounting time ? ?odules time ? ?odules will be tu? ned off input/output po?ts i/o po?ts will be setup as inputs sta?k pointe? sta?k pointe? will point to t?e top of t?e sta?k the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects the microcontroller internal registers.
rev. 1.00 74 ?a??? 1?? ?01? rev. 1.00 75 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom register reset status table register ht69f30a ht69f40a HT69F50A power-on reset res or lvr reset wdt time-out (normal operation) wdt time-out (halt) iar0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ?p0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu iar1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ?p1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu bp ---- ---0 ---- ---0 ---- ---0 ---- ---u bp ---- --00 ---- --00 ---- --00 ---- --uu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp ---- -xxx ---- -uuu ---- -uuu ---- -uuu tbhp ---- xxxx ---- uuuu ---- uuuu ---- uuuu tbhp ---x xxxx ---u uuuu ---u uuuu ---u uuuu status --00 xxxx --uu uuuu --1u uuuu --11 uuuu s?od 0000 0011 0000 0011 0000 0011 uuuu uuuu lvdc --00 -000 --00 -000 --00 -000 --uu -uuu integ --00 0000 --00 0000 --00 0000 --uu uuuu wdtc 0101 0011 0101 0011 0101 0011 uuuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu intc0 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu s?od1 0--- -x00 0--- -1uu 0--- -uuu u--- -uuu lvrc 0101 0101 uuuu uuuu 0101 0101 uuuu uuuu ?fi0 --00 --00 --00 --00 --00 --00 --uu --uu ?fi0 0000 0000 0000 0000 0000 0000 uuuu uuuu ?fi1 -000 -000 -000 -000 -000 -000 -uuu -uuu ?fi? --00 --00 --00 --00 --00 --00 --uu --uu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu ---- 0000 ---- 0000 ---- 0000 ---- uuuu pbpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pb ---- 1111 ---- 1111 ---- 1111 ---- uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc ---- 1111 ---- 1111 ---- 1111 ---- uuuu pbc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcpu ---- -000 ---- -000 ---- -000 ---- -uuu pcpu -000 0000 -000 0000 -000 0000 -uuu uuuu
rev. 1.00 76 ?a??? 1?? ?01? rev. 1.00 77 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom register ht69f30a ht69f40a HT69F50A power-on reset res or lvr reset wdt time-out (normal operation) wdt time-out (halt) pc ---- -111 ---- -111 ---- -111 ---- -uuu pc -111 1111 -111 1111 -111 1111 -uuu uuuu pcc ---- -111 ---- -111 ---- -111 ---- -uuu pcc -111 1111 -111 1111 -111 1111 -uuu uuuu pdpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 uuuu uuuu pepu 0000 0000 0000 0000 0000 0000 uuuu uuuu pe 1111 1111 1111 1111 1111 1111 uuuu uuuu pec 1111 1111 1111 1111 1111 1111 uuuu uuuu pfpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pf 1111 1111 1111 1111 1111 1111 uuuu uuuu pfc 1111 1111 1111 1111 1111 1111 uuuu uuuu pgpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pg 1111 1111 1111 1111 1111 1111 uuuu uuuu pgc 1111 1111 1111 1111 1111 1111 uuuu uuuu phpu 0000 0000 0000 0000 0000 0000 uuuu uuuu ph 1111 1111 1111 1111 1111 1111 uuuu uuuu phc 1111 1111 1111 1111 1111 1111 uuuu uuuu pafs -00- 0-0- -00- 0-0- -00- 0-0- -uu- u-u- pbfs 0000 ---- 0000 ---- 0000 ---- uuuu ---- pcfs ---- -000 ---- -000 ---- -000 ---- -uuu pdfs 1111 1111 1111 1111 1111 1111 uuuu uuuu pefs 1111 1111 1111 1111 1111 1111 uuuu uuuu pffs 1111 1111 1111 1111 1111 1111 uuuu uuuu pgfs 1111 1111 1111 1111 1111 1111 uuuu uuuu phfs 1111 1111 1111 1111 1111 1111 uuuu uuuu sfs -000 ---- -000 ---- -000 ---- -uuu ---- sfs 0000 0000 0000 0000 0000 0000 uuuu uuuu t?0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu t?0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t?0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t?0dh ---- --00 ---- --00 ---- --00 ---- --uu t?0al 0000 0000 0000 0000 0000 0000 uuuu uuuu t?0ah ---- --00 ---- --00 ---- --00 ---- --uu eec ---- 0000 ---- 0000 ---- 0000 ---- uuuu eea --00 0000 --00 0000 --00 0000 --uu uuuu eea -000 0000 -000 0000 -000 0000 -uuu uuuu eed 0000 0000 0000 0000 0000 0000 uuuu uuuu t?1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu
rev. 1.00 76 ?a??? 1?? ?01? rev. 1.00 77 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom register ht69f30a ht69f40a HT69F50A power-on reset res or lvr reset wdt time-out (normal operation) wdt time-out (halt) t?1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t?1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t?1dh ---- --00 ---- --00 ---- --00 ---- --uu t?1al 0000 0000 0000 0000 0000 0000 uuuu uuuu t?1ah ---- --00 ---- --00 ---- --00 ---- --uu t?1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu t?1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t?1c? 0000 0000 0000 0000 0000 0000 uuuu uuuu t?1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t?1dh ---- --00 ---- --00 ---- --00 ---- --uu t?1al 0000 0000 0000 0000 0000 0000 uuuu uuuu t?1ah ---- --00 ---- --00 ---- --00 ---- --uu t?1bl 0000 0000 0000 0000 0000 0000 uuuu uuuu t?1bh ---- --00 ---- --00 ---- --00 ---- --uu t??c0 0000 0000 0000 0000 0000 0000 uuuu uuuu t??c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t??dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t??dh ---- --00 ---- --00 ---- --00 ---- --uu t??al 0000 0000 0000 0000 0000 0000 uuuu uuuu t??ah ---- --00 ---- --00 ---- --00 ---- --uu t??c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- t??c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t??dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t??dh 0000 0000 0000 0000 0000 0000 uuuu uuuu t??al 0000 0000 0000 0000 0000 0000 uuuu uuuu t??ah 0000 0000 0000 0000 0000 0000 uuuu uuuu t??rp 0000 0000 0000 0000 0000 0000 uuuu uuuu lcdc 0-0- 0000 0-0- 0000 0-0- 0000 u-u- uuuu note: - not implement u means unchanged x means unknown
rev. 1.00 78 ?a??? 1?? ?01? rev. 1.00 7? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom input/output ports holtek microcontrollers offer considerable fexibility on their i/o ports. with the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names pa~ph. these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o port register list ht69f30a register name bit 7 6 5 4 3 2 1 0 pawu pawu7 pawu6 pawu5 pawu4 pawu ? pawu ? pawu1 pawu0 papu papu7 papu6 papu5 papu4 papu ? papu ? papu1 papu0 pa pa7 pa6 pa5 pa4 pa ? pa ? pa1 pa0 pac pac7 pac6 pac5 pac4 pac ? pac ? pac1 pac0 pbpu pbpu? pbpu? pbpu1 pbpu0 pb pb? pb? pb1 pb0 pbc pbc? pbc? pbc1 pbc0 pcpu pcpu? pcpu1 pcpu0 pc pc? pc1 pc0 pcc pcc? pcc1 pcc0 pdpu pdpu7 pdpu6 pdpu5 pdpu4 pdpu? pdpu? pdpu1 pdpu0 pd pd7 pd6 pd5 pd4 pd? pd? pd1 pd0 pdc pdc7 pdc6 pdc5 pdc4 pdc? pdc? pdc1 pdc0 pepu pepu7 pepu6 pepu5 pepu4 pepu? pepu? pepu1 pepu0 pe pe7 pe6 pe5 pe4 pe? pe? pe1 pe0 pec pec7 pec6 pec5 pec4 pec? pec? pec1 pec0 pfpu pfpu7 pfpu6 pfpu5 pfpu4 pfpu? pfpu? pfpu1 pfpu0 pf pf7 pf6 pf5 pf4 pf? pf? pf1 pf0 pfc pfc7 pfc6 pfc5 pfc4 pfc? pfc? pfc1 pfc0
rev. 1.00 78 ?a??? 1?? ?01? rev. 1.00 7? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f40a register name bit 7 6 5 4 3 2 1 0 pawu pawu7 pawu6 pawu5 pawu4 pawu ? pawu ? pawu1 pawu0 papu papu7 papu6 papu5 papu4 papu ? papu ? papu1 papu0 pa pa7 pa6 pa5 pa4 pa ? pa ? pa1 pa0 pac pac7 pac6 pac5 pac4 pac ? pac ? pac1 pac0 pbpu pbpu7 pbpu6 pbpu5 pbpu4 pbpu? pbpu? pbpu1 pbpu0 pb pb7 pb6 pb5 pb4 pb? pb? pb1 pb0 pbc pbc7 pbc6 pbc5 pbc4 pbc? pbc? pbc1 pbc0 pcpu pcpu6 pcpu5 pcpu4 pcpu? pcpu? pcpu1 pcpu0 pc pc6 pc5 pc4 pc? pc? pc1 pc0 pcc pcc6 pcc4 pcc4 pcc? pcc? pcc1 pcc0 pdpu pdpu7 pdpu6 pdpu5 pdpu4 pdpu? pdpu? pdpu1 pdpu0 pd pd7 pd6 pd5 pd4 pd? pd? pd1 pd0 pdc pdc7 pdc6 pdc5 pdc4 pdc? pdc? pdc1 pdc0 pepu pepu7 pepu6 pepu5 pepu4 pepu? pepu? pepu1 pepu0 pe pe7 pe6 pe5 pe4 pe? pe? pe1 pe0 pec pec7 pec6 pec5 pec4 pec? pec? pec1 pec0 pfpu pfpu7 pfpu6 pfpu5 pfpu4 pfpu? pfpu? pfpu1 pfpu0 pf pf7 pf6 pf5 pf4 pf? pf? pf1 pf0 pfc pfc7 pfc6 pfc5 pfc4 pfc? pfc? pfc1 pfc0 pgpu pgpu7 pgpu6 pgpu5 pgpu4 pgpu? pgpu? pgpu1 pgpu0 pg pg7 pg6 pg5 pg4 pg? pg? pg1 pg0 pgc pgc7 pgc6 pgc5 pgc4 pgc? pgc? pgc1 pgc0
rev. 1.00 80 ?a??? 1?? ?01? rev. 1.00 81 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom HT69F50A register name bit 7 6 5 4 3 2 1 0 pawu pawu7 pawu6 pawu5 pawu4 pawu ? pawu ? pawu1 pawu0 papu papu7 papu6 papu5 papu4 papu ? papu ? papu1 papu0 pa pa7 pa6 pa5 pa4 pa ? pa ? pa1 pa0 pac pac7 pac6 pac5 pac4 pac ? pac ? pac1 pac0 pbpu pbpu7 pbpu6 pbpu5 pbpu4 pbpu? pbpu? pbpu1 pbpu0 pb pb7 pb6 pb5 pb4 pb? pb? pb1 pb0 pbc pbc7 pbc6 pbc5 pbc4 pbc? pbc? pbc1 pbc0 pcpu pcpu6 pcpu5 pcpu4 pcpu? pcpu? pcpu1 pcpu0 pc pc6 pc5 pc4 pc? pc? pc1 pc0 pcc pcc6 pcc4 pcc4 pcc? pcc? pcc1 pcc0 pdpu pdpu7 pdpu6 pdpu5 pdpu4 pdpu? pdpu? pdpu1 pdpu0 pd pd7 pd6 pd5 pd4 pd? pd? pd1 pd0 pdc pdc7 pdc6 pdc5 pdc4 pdc? pdc? pdc1 pdc0 pepu pepu7 pepu6 pepu5 pepu4 pepu? pepu? pepu1 pepu0 pe pe7 pe6 pe5 pe4 pe? pe? pe1 pe0 pec pec7 pec6 pec5 pec4 pec? pec? pec1 pec0 pfpu pfpu7 pfpu6 pfpu5 pfpu4 pfpu? pfpu? pfpu1 pfpu0 pf pf7 pf6 pf5 pf4 pf? pf? pf1 pf0 pfc pfc7 pfc6 pfc5 pfc4 pfc? pfc? pfc1 pfc0 pgpu pgpu7 pgpu6 pgpu5 pgpu4 pgpu? pgpu? pgpu1 pgpu0 pg pg7 pg6 pg5 pg4 pg? pg? pg1 pg0 pgc pgc7 pgc6 pgc5 pgc4 pgc? pgc? pgc1 pgc0 phpu phpu7 phpu6 phpu5 phpu4 phpu? phpu? phpu1 phpu0 ph ph7 ph6 ph5 ph4 ph? ph? ph1 ph0 phc phc7 phc6 phc5 phc4 phc? phc? phc1 phc0 unimplemented, read as 0 pawun: pa wake-up function control 0: disable 1: enable pan/pbn/pcn/pdn/pen/pfn/pgn/phn: i/o data bit 0: data 0 1: data 1 pacn/pbcn/pccn/pdcn/pecn/pfcn/pgcn/phcn: i/o type selection 0: output 1: input papun/pbpun/pcpun/pdpun/pepun/pfpun/pgpun/phpun: pull-high function control 0: disable 1: enable
rev. 1.00 80 ?a??? 1?? ?01? rev. 1.00 81 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selected using registers papu~phpu, and are implemented using weak pmos transistors. port a wake-up the halt instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low. this function is especially suitable for applications that can be woken up via external switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. i/o port control registers each port has its own control register, known as pac~phc, which controls the input/output configuration. with this control register, each i/o pin with or without pull-high resistors can be reconfigured dynamically under software control. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pin-shared functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these diffculties can be overcome. for these pins, the chosen function of the multi-function i/o pins is selected by a series of regiters via the application program control.
rev. 1.00 8? ?a??? 1?? ?01? rev. 1.00 8? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pin-shared function selection register list ? ht69f30a register name bit 7 6 5 4 3 2 1 0 pafs pafs6 pafs5 pafs ? pafs1 pcfs pcfs? pcfs1 pcfs0 pdfs pdfs7 pdfs6 pdfs5 pdfs4 pdfs? pdfs? pdfs1 pdfs0 pefs pefs7 pefs6 pefs5 pefs4 pefs? pefs? pefs1 pefs0 pffs pffs7 pffs6 pffs5 pffs4 pffs? pffs? pffs1 pffs0 sfs sfs6 sfs5 sfs4 ? ht69f40a register name bit 7 6 5 4 3 2 1 0 pafs pafs6 pafs5 pafs ? pafs1 pbfs pbfs7 pbfs6 pbfs5 pbfs4 pcfs pcfs? pcfs1 pcfs0 pdfs pdfs7 pdfs6 pdfs5 pdfs4 pdfs? pdfs? pdfs1 pdfs0 pefs pefs7 pefs6 pefs5 pefs4 pefs? pefs? pefs1 pefs0 pffs pffs7 pffs6 pffs5 pffs4 pffs? pffs? pffs1 pffs0 pgfs pgs7 pfgfs6 pgfs5 pgfs4 pgfs? pgfs? pgfs1 pgfs0 sfs sfs7 sfs6 sfs5 sfs4 sfs? sfs? sfs1 sfs0 ? HT69F50A register name bit 7 6 5 4 3 2 1 0 pafs pafs6 pafs5 pafs ? pafs1 pbfs pbfs7 pbfs6 pbfs5 pbfs4 pcfs pcfs? pcfs1 pcfs0 pdfs pdfs7 pdfs6 pdfs5 pdfs4 pdfs? pdfs? pdfs1 pdfs0 pefs pefs7 pefs6 pefs5 pefs4 pefs? pefs? pefs1 pefs0 pffs pffs7 pffs6 pffs5 pffs4 pffs? pffs? pffs1 pffs0 pgfs pgs7 pgfs6 pgfs5 pgfs4 pgfs? pgfs? pgfs1 pgfs0 phfs phs7 phfs6 phfs5 phfs4 phfs? phfs? phfs1 phfs0 sfs sfs7 sfs6 sfs5 sfs4 sfs? sfs? sfs1 sfs0
rev. 1.00 8? ?a??? 1?? ?01? rev. 1.00 8? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pafs register C ht69f30a bit 7 6 5 4 3 2 1 0 name pafs6 pafs5 pafs ? pafs1 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 pafs6: port a 6 function selection 0: i/o 1: tp0_0 bit 5 pafs5: port a 5 function selection 0: i/o 1: tp1_1 bit 4 unimplemented, read as 0 bit 3 pafs3: port a 3 function selection 0: i/o 1: tp1_0 bit 2 unimplemented, read as 0 bit 1 pafs1: port a 1 function selection 0: i/o 1: tp0_1 bit 0 unimplemented, read as 0 pafs register C ht69f40a/HT69F50A bit 7 6 5 4 3 2 1 0 name pafs6 pafs5 pafs ? pafs1 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 pafs6: port a 6 function selection 0: i/o 1: tp0_0 bit 5 pafs5: port a 5 function selection 0: i/o 1: tp2_1 bit 4 unimplemented, read as 0 bit 3 pafs3: port a 3 function selection 0: i/o 1: tp2_0 bit 2 unimplemented, read as 0 bit 1 pafs1: port a 1 function selection 0: i/o 1: tp0_1 bit 0 unimplemented, read as 0
rev. 1.00 84 ?a??? 1?? ?01? rev. 1.00 85 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pbfs register C ht69f40a/HT69F50A bit 7 6 5 4 3 2 1 0 name pbfs7 pbfs6 pbfs5 pbfs4 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 pbfs7: port b 7 function selection 0: i/o 1: tp1b_2 bit 6 pbfs6: port b 6 function selection 0: i/o 1: tp1b_1 bit 5 pbfs5: port b 5 function selection 0: i/o 1: tp1b_0 bit 4 pbfs4: port b 4 function selection 0: i/o 1: tp1a bit 3~0 unimplemented, read as 0 pcfs register C ht69f30a/ht69f40a/HT69F50A bit 7 6 5 4 3 2 1 0 name pcfs? pcfs1 pcfs0 r/w r/w r/w r/w por 0 0 0 bit 7~3 unimplemented, read as 0 bit 2 pcfs2: port c 2 function selection 0: i/o 1: c2 bit 1 pcfs1: port c 1 function selection 0: i/o 1: c1 bit 0 pcfs0: port c 0 function selection 0: i/o 1: v2
rev. 1.00 84 ?a??? 1?? ?01? rev. 1.00 85 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pdfs register C ht69f30a bit 7 6 5 4 3 2 1 0 name pdfs7 pdfs6 pdfs5 pdfs4 pdfs? pdfs? pdfs1 pdfs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 pdfs7: port d 7 function selection 0: i/o 1: seg7 bit 6 pdfs6: port d 6 function selection 0: i/o 1: seg6 bit 5 pdfs5: port d 5 function selection 0: i/o 1: seg5 bit 4 pdfs4: port d 4 function selection 0: i/o 1: seg4 bit 3 pdfs3: port d 3 function selection 0: i/o 1: seg3 bit 2 pdfs2: port d 2 function selection 0: i/o 1: seg2 bit 1 pdfs1: port d 1 function selection 0: i/o 1: seg1 bit 0 pdfs0: port d 0 function selection 0: i/o 1: seg0
rev. 1.00 86 ?a??? 1?? ?01? rev. 1.00 87 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pdfs register C ht69f40a/HT69F50A bit 7 6 5 4 3 2 1 0 name pdfs7 pdfs6 pdfs5 pdfs4 pdfs? pdfs? pdfs1 pdfs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 pdfs7: port d 7 function selection 0: i/o 1: seg7 or tp1b_2 bit 6 pdfs6: port d 6 function selection 0: i/o 1: seg6 or tp1b_1 bit 5 pdfs5: port d 5 function selection 0: i/o 1: seg5 or tp1b_0 bit 4 pdfs4: port d 4 function selection 0: i/o 1: seg4 or tp1a bit 3 pdfs3: port d 3 function selection 0: i/o 1: seg3 bit 2 pdfs2: port d 2 function selection 0: i/o 1: seg2 bit 1 pdfs1: port d 1 function selection 0: i/o 1: seg1 bit 0 pdfs0: port d 0 function selection 0: i/o 1: seg0
rev. 1.00 86 ?a??? 1?? ?01? rev. 1.00 87 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pefs register C ht69f30a/ht69f40a/HT69F50A bit 7 6 5 4 3 2 1 0 name pefs7 pefs6 pefs5 pefs4 pefs? pefs? pefs1 pefs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 pefs7: port e 7 function selection 0: i/o 1: seg15 bit 6 pefs6: port e 6 function selection 0: i/o 1: seg14 bit 5 pefs5: port e 5 function selection 0: i/o 1: seg13 bit 4 pefs4: port e 4 function selection 0: i/o 1: seg12 bit 3 pefs3: port e 3 function selection 0: i/o 1: seg11 bit 2 pefs2: port e 2 function selection 0: i/o 1: seg10 bit 1 pefs1: port e 1 function selection 0: i/o 1: seg9 bit 0 pefs0: port e 0 function selection 0: i/o 1: seg8
rev. 1.00 88 ?a??? 1?? ?01? rev. 1.00 8? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pffs register C ht69f30a/ht69f40a/HT69F50A bit 7 6 5 4 3 2 1 0 name pffs7 pffs6 pffs5 pffs4 pffs? pffs? pffs1 pffs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 pffs7: port f 7 function selection 0: i/o 1: seg23 bit 6 pffs6: port f 6 function selection 0: i/o 1: seg22 bit 5 pffs5: port f 5 function selection 0: i/o 1: seg21 bit 4 pffs4: port f 4 function selection 0: i/o 1: seg20 bit 3 pffs3: port f 3 function selection 0: i/o 1: seg19 bit 2 pffs2: port f 2 function selection 0: i/o 1: seg18 bit 1 pffs1: port f 1 function selection 0: i/o 1: seg17 bit 0 pffs0: port f 0 function selection 0: i/o 1: seg16
rev. 1.00 88 ?a??? 1?? ?01? rev. 1.00 8? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pgfs register C ht69f40a/HT69F50A bit 7 6 5 4 3 2 1 0 name pgfs7 pgfs6 pgfs5 pgfs4 pgfs? pgfs? pgfs1 pgfs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 pgfs7: port g 7 function selection 0: i/o 1: seg31 bit 6 pgfs6: port g 6 function selection 0: i/o 1: seg30 bit 5 pgfs5: port g 5 function selection 0: i/o 1: seg29 bit 4 pgfs4: port g 4 function selection 0: i/o 1: seg28 bit 3 pgfs3: port g 3 function selection 0: i/o 1: seg27 bit 2 pgfs2: port g 2 function selection 0: i/o 1: seg26 bit 1 pgfs1: port g 1 function selection 0: i/o 1: seg25 bit 0 pgfs0: port g 0 function selection 0: i/o 1: seg24
rev. 1.00 ?0 ?a??? 1?? ?01? rev. 1.00 ?1 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom phfs register C HT69F50A bit 7 6 5 4 3 2 1 0 name phfs7 phfs6 phfs5 phfs4 phfs? phfs? phfs1 phfs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 phfs7: port h 7 function selection 0: i/o 1: seg39 bit 6 phfs6: port h 6 function selection 0: i/o 1: seg38 bit 5 phfs5: port h 5 function selection 0: i/o 1: seg37 bit 4 phfs4: port h 4 function selection 0: i/o 1: seg36 bit 3 phfs3: port h 3 function selection 0: i/o 1: seg35 bit 2 phfs2: port h 2 function selection 0: i/o 1: seg34 bit 1 phfs1: port h 1 function selection 0: i/o 1: seg33 bit 0 phfs0: port h 0 function selection 0: i/o 1: seg32 sfs register C ht69f30a bit 7 6 5 4 3 2 1 0 name sfs6 sfs5 sfs4 r/w r/w r/w r/w por 0 0 0 bit 7 unimplemented, read as 0 bit 6 sfs6: tck1 source selection 0: pa2 1: pd2 bit 5 sfs5: tck0 source selection 0: pa2 1: pd1 bit 4 sfs4: int1 source selection 0: pa0 1: pd0 bit 3~0 unimplemented, read as 0
rev. 1.00 ?0 ?a??? 1?? ?01? rev. 1.00 ?1 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom sfs register C ht69f40a/HT69F50A bit 7 6 5 4 3 2 1 0 name sfs7 sfs6 sfs5 sfs4 sfs? sfs? sfs1 sfs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 sfs7: tck2 source selection 0: pa2 1: pd2 bit 6 sfs6: tck1 source selection 0: pa0 1: pd3 bit 5 sfs5: tck0 source selection 0: pa2 1: pd1 bit 4 sfs4: int1 source selection 0: pa0 1: pd0 bit 3 sfs3: pd7 special function selection 0: seg7 1: tp1b_2 bit 2 sfs2: pd6 special function selection 0: seg6 1: tp1b_1 bit 1 sfs1: pd5 special function selection 0: seg5 1: tp1b_0 bit 0 sfs0: pd4 special function selection 0: seg4 1: tp1a
rev. 1.00 ?? ?a??? 1?? ?01? rev. 1.00 ?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown. programming considerations within the user program, one of the things frst to consider is port initialisation. after a reset, all of the i/o data and port control registers will be set to high. this means that all i/o pins will be defaulted to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function.

??? ?? ? ? ? generic input/output structure
rev. 1.00 ?? ?a??? 1?? ?01? rev. 1.00 ?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. to implement time related functions each device includes several timer modules, abbreviated to the name tm. the tms are multi-purpose timing units and serve to provide operations such as timer/counter, input capture, compare match output and single pulse output as well as being the functional unit for the generation of pwm signals. each of the tms has either two or three individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the different tm types are described here with more detailed information provided in the individual compact, standard and enhanced tm sections. introduction the devices contain from two to three tms depending upon which device is selected with each tm having a reference name of tm0, tm1, and tm2. each individual tm can be categorised as a certain type, namely compact type tm, standard type tm or enhanced type tm. although similar in nature, the different tm types vary in their feature complexity. the common features to all of the compact, standard and enhanced tms will be described in this section, the detailed operation regarding each of the tm types will be described in separate sections. the main features and differences between the three types of tms are summarised in the accompanying table. tm function ctm stm etm time ?/counte? i/p captu ?e compa?e ?at?? output pw? c?annels 1 1 ? single pulse output 1 ? pw? alignment edge edge edge & cent?e pw? adjustment pe?iod & duty duty o? pe?iod duty o? pe?iod duty o? pe?iod tm function summary each device in the series contains a specifc number of either compact type, standard type and enhanced type tm unit which are shown in the table together with their individual reference name, tm0~tm2. device tm0 tm1 tm2 ht6?f?0a 10-bit ct? 10-bit st? ht6?f40a 10-bit ct? 10-bit et? 10-bit st? ht6?f50a 10-bit ct? 10-bit et? 16-bit st? tm name/type reference tm operation the three different types of tm offer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. when the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a tm interrupt signal will be generated which can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable clock source, which can be an internal clock or an external pin.
rev. 1.00 ?4 ?a??? 1?? ?01? rev. 1.00 ?5 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom tm clock source the clock source which drives the main counter in each tm can originate from various sources. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tmn control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f sub clock source or the external tckn pin. note that setting these bits to the value 101 will select a reserved clock input, in effect disconnecting the tm clock source. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the compact and standard type tms each have two internal interrupts, one for each of the internal comparator a or comparator p, which generate a tm interrupt when a compare match condition occurs. as the enhanced type tm has three internal comparators and comparator a or comparator b or comparator p compare match functions, it consequently has three internal interrupts. when a tm interrupt is generated it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin, is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register. this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm if selected using the tnck2~tnck0 bits. the tm input pin can be chosen to have either a rising or falling active edge. the tms each have one or more output pins with the label tpn. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must first be setup using registers. a single bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. the number of output pins for each tm type and device is different, the details are provided in the accompanying table. all tm output pin names have a _n suffx. pin names that include a _1 or _2 suffx indicate that they are from a tm with multiple output pins. this allows the tm to generate a complimentary output pair, selected using the i/o register data bits. device ctm stm etm registers ht6?f?0a tp0_0?tp0_1 tp1_0?tp1_1 pafs ht6?f40a tp0_0?tp0_1 tp?_0?tp?_1 tp1a? tp1b_0? tp1b_1? tp1b_? pafs ? pbfs? pdfs ht6?f50a tp0_0?tp0_1 tp?_0?tp?_1 tp1a? tp1b_0? tp1b_1? tp1b_? pafs ? pbfs? pdfs tm output pins
rev. 1.00 ?4 ?a??? 1?? ?01? rev. 1.00 ?5 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom tm input/output pin control registers selecting to have a tm input/output or whether to retain its other shared function, is implemented using one or two registers, with a single bit in each register corresponding to a tm input/output pin. setting the bit high will setup the corresponding pin as a tm input/output, if reset to zero the pin will retain its original other function. tm input/output pin control register list ? ht69f30a register name bit 7 6 5 4 3 2 1 0 pafs pafs6 pafs5 pafs ? pafs1 sfs sfs6 sfs5 sfs4 ? ht69f40a/HT69F50A register name bit 7 6 5 4 3 2 1 0 pafs pafs6 pafs5 pafs ? pafs1 pbfs pbfs7 pbfs6 pbfs5 pbfs4 pdfs pdfs7 pdfs6 pdfs5 pdfs4 pdfs? pdfs? pdfs1 pdfs0 sfs sfs7 sfs6 sfs5 sfs4 sfs? sfs? sfs1 sfs0 pafs register C ht69f30a bit 7 6 5 4 3 2 1 0 name pafs6 pafs5 pafs ? pafs1 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 pafs6: port a 6 function selection 0: i/o 1: tp0_0 bit 5 pafs5: port a 5 function selection 0: i/o 1: tp1_1 bit 4 unimplemented, read as 0 bit 3 pafs3: port a 3 function selection 0: i/o 1: tp1_0 bit 2 unimplemented, read as 0 bit 1 pafs1: port a 1 function selection 0: i/o 1: tp0_1 bit 0 unimplemented, read as 0
rev. 1.00 ?6 ?a??? 1?? ?01? rev. 1.00 ?7 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pafs register C ht69f40a/HT69F50A bit 7 6 5 4 3 2 1 0 name pafs6 pafs5 pafs ? pafs1 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 pafs6: port a 6 function selection 0: i/o 1: tp0_0 bit 5 pafs5: port a 5 function selection 0: i/o 1: tp2_1 bit 4 unimplemented, read as 0 bit 3 pafs3: port a 3 function selection 0: i/o 1: tp2_0 bit 2 unimplemented, read as 0 bit 1 pafs1: port a 1 function selection 0: i/o 1: tp0_1 bit 0 unimplemented, read as 0 pbfs register C ht69f40a/HT69F50A bit 7 6 5 4 3 2 1 0 name pbfs7 pbfs6 pbfs5 pbfs4 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 pbfs7: port b 7 function selection 0: i/o 1: tp1b_2 bit 6 pbfs6: port b 6 function selection 0: i/o 1: tp1b_1 bit 5 pbfs5: port b 5 function selection 0: i/o 1: tp1b_0 bit 4 pbfs4: port b 4 function selection 0: i/o 1: tp1a bit 3~0 unimplemented, read as 0
rev. 1.00 ?6 ?a??? 1?? ?01? rev. 1.00 ?7 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom pdfs register C ht69f40a/HT69F50A bit 7 6 5 4 3 2 1 0 name pdfs7 pdfs6 pdfs5 pdfs4 pdfs? pdfs? pdfs1 pdfs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 pdfs7: port d 7 function selection 0: i/o 1: seg7 or tp1b_2 bit 6 pdfs6: port d 6 function selection 0: i/o 1: seg6 or tp1b_1 bit 5 pdfs5: port d 5 function selection 0: i/o 1: seg5 or tp1b_0 bit 4 pdfs4: port d 4 function selection 0: i/o 1: seg4 or tp1a bit 3~0 pdfs3~pdfs0: port d 3~0 function selection described elsewhere. sfs register C ht69f30a bit 7 6 5 4 3 2 1 0 name sfs6 sfs5 sfs4 r/w r/w r/w r/w por 0 0 0 bit 7 unimplemented, read as 0 bit 6 sfs6: tck1 source selection 0: pa2 1: pd2 bit 5 sfs5: tck0 source selection 0: pa2 1: pd1 bit 4 sfs4: int1 source selection described elsewhere. bit 3~0 unimplemented, read as 0
rev. 1.00 ?8 ?a??? 1?? ?01? rev. 1.00 ?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom sfs register C ht69f40a/HT69F50A bit 7 6 5 4 3 2 1 0 name sfs7 sfs6 sfs5 sfs4 sfs? sfs? sfs1 sfs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 sfs7: tck2 source selection 0: pa2 1: pd2 bit 6 sfs6: tck1 source selection 0: pa0 1: pd3 bit 5 sfs5: tck0 source selection 0: pa2 1: pd1 bit 4 sfs4: int1 source selection described elsewhere. bit 3 sfs3: pd7 special function selection 0: seg7 1: tp1b_2 bit 2 sfs2: pd6 special function selection 0: seg6 1: tp1b_1 bit 1 sfs1: pd5 special function selection 0: seg5 1: tp1b_0 bit 0 sfs0: pd4 special function selection 0: seg4 1: tp1a
rev. 1.00 ?8 ?a??? 1?? ?01? rev. 1.00 ?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom t?0 (ct?) 0 1 0 1 pa6/tp0_0 pa1/tp0_1 pa? o? pd1/tck0 pa6 pa1 0 1 0 1 pafs6 pafs? pa1 pa6 output tck0 input ctm function pin control block diagram C ht69f30a/ht69f40a/HT69F50A t?n (st?) 0 1 0 1 pa?/tpn_0 pa5/tpn_1 pa? o? pd?/tckn pa? pa5 0 1 0 1 pafs? pafs5 pa5 pa? pafs? pafs5 captu?e input tckn input output 0 0 1 0 1 0 stm function pin control block diagram C ht69f30a (n=1); ht69f40a/HT69F50A (n=2)
rev. 1.00 100 ?a??? 1?? ?01? rev. 1.00 101 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom t?1 (et?) 0 1 0 1 pa0 o? pd?/tck1 0 1 0 1 ccrb captu?e input 1 0 1 0 1 0 0 1 0 1 0 pb5 o? pd5/tp1b_0 0 0 tck1 input 0 1 pb4? pd4 0 ccrb output ccra captu?e input ccra output pb4 o? pd4/tp1a pbfs4? pdfs4 1 0 pbfs4? pdfs4 pb5? pd5 pb5? pd5 pbfs5? pdfs5 pb6? pd6 pb6? pd6 pbfs6? pdfs6 pb7? pd7 pb7? pd7 pbfs7? pdfs7 pbfs7? pdfs7 pbfs6? pdfs6 pbfs5? pdfs5 pb6 o? pd6/tp1b_1 pb7 o? pd7/tp1b_? etm function pin control block diagram C ht69f40a/HT69F50A note: the i/o register data bits shown are used for tm output inversion control. in the capture input mode, the tm pin control register must never enable more than one tm input.
rev. 1.00 100 ?a??? 1?? ?01? rev. 1.00 101 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom programming considerations the tm counter registers and the capture/compare ccra and ccrb registers, being either 10-bit or 16-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specifc way. the important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra and ccrb registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specifc way described above, it is recommended to use the mov instruction to access the ccra and ccrb low byte registers, named tmxal and tmxbl, using the following access procedures. accessing the ccra or ccrb low byte registers without following these access procedures will result in unpredictable values. data bus 8 - bit buffe? t?xdh t?xdl t?xbh t?xbl t?xah t?xal t? counte? registe? ( read only ) t? ccra registe? ( read / w?ite ) t? ccrb registe? ( read / w?ite ) the following steps show the read and write procedures: ? writing data to ccrb or ccra ? step 1. write data to low byte tmxal or tmxbl C note that here data is only written to the 8-bit buffer. ? step 2. write data to high byte tmxah or tmxbh C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccrb or ccra ? step 1. read data from the high byte tmxdh, tmxah or tmxbh C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl, tmxal or tmxbl C this step reads data from the 8-bit buffer.
rev. 1.00 10? ?a??? 1?? ?01? rev. 1.00 10? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom compact type tm C ctm although the simplest form of the three tm types, the compact tm type still contains three operating modes, which are compare match output, timer/event counter and pwm output modes. the compact tm can also be controlled with an external input pin and can drive one or two external output pins. these two external output pins can be the same signal or the inverse signal. device tm type tm name. tm input pin tm output pin ht6?f?0a ht6?f40a ht6?f50a 10-bit ct? t?0 tck0 tp0_0? tp0_1
? ? ? ? ? ? ? ? ? ?
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? - - ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? ? ? ?? ? ?? compact type tm block diagram (n=0) compact tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
rev. 1.00 10? ?a??? 1?? ?01? rev. 1.00 10? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom compact type tm register description overall operation of the compact tm is controlled using six registers. a read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t?nc0 tnpau tnck? tnck1 tnck0 tnon tnrp? tnrp1 tnrp0 t?nc1 tn?1 tn?0 tnio1 tnio0 tnoc tnpol tndpx tncclr t?ndl d7 d6 d5 d4 d? d? d1 d0 t?ndh d? d8 t?nal d7 d6 d5 d4 d? d? d1 d0 t?nah d? d8 compact tm register list (n=0) tmndl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tmndl : tmn counter low byte register bit 7 ~ bit 0 tmn 10-bit counter bit 7 ~ bit 0 tmndh register bit 7 6 5 4 3 2 1 0 name d? d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tmndh : tmn counter high byte register bit 1 ~ bit 0 tmn 10-bit counter bit 9 ~ bit 8 tmnal register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tmnal : tmn ccra low byte register bit 7 ~ bit 0 tmn 10-bit ccra bit 7 ~ bit 0 tmnah register bit 7 6 5 4 3 2 1 0 name d? d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tmnah : tmn ccra high byte register bit 1 ~ bit 0 tmn 10-bit ccra bit 9 ~ bit 8
rev. 1.00 104 ?a??? 1?? ?01? rev. 1.00 105 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom tmnc0 register bit 7 6 5 4 3 2 1 0 name tnpau tnck? tnck1 tnck0 tnon tnrp? tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tnpau: tmn counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0: select tmn counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f sub 101: reserved 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f sub are other internal clocks, the details of which can be found in the oscillator section. bit 3 tnon: tmn counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high.
rev. 1.00 104 ?a??? 1?? ?01? rev. 1.00 105 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom bit 2~0 tnrp2~tnrp0: tmn ccrp 3-bit register, compared with the tmn counter bit 9~bit 7 comparator p match period 000: 1024 tmn clocks 001: 128 tmn clocks 010: 256 tmn clocks 011: 384 tmn clocks 100: 512 tmn clocks 101: 640 tmn clocks 110: 768 tmn clocks 111: 896 tmn clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counter's highest three bits. the result of this comparison can be selected to clear the internal counter if the tncclr bit is set to zero. setting the tncclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. tmnc1 register bit 7 6 5 4 3 2 1 0 name tn?1 tn?0 tnio1 tnio0 tnoc tnpol tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 tnm1~tnm0 : select tmn operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the tnm1 and tnm0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 tnio1~tnio0 : select tpn_0, tpn_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running.
rev. 1.00 106 ?a??? 1?? ?01? rev. 1.00 107 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom in the compare match output mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit in the tmnc1 register. note that the output level requested by the tnio1 and tnio0 bits must be different from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to only change the values of the tnio1 and tnio0 bits only after the tmn has been switched off. unpredictable pwm outputs will occur if the tnio1 and tnio0 bits are changed when the tm is running. bit 3 tnoc : tpn_0, tpn_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 tnpol : tpn_0, tpn_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn_0 or tpn_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 tndpx : tmn pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 tncclr : select tmn counter clear condition 0: tmn comparatror p match 1: tmn comparatror a match this bit is used to select the method which clears the counter. remember that the compact tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm mode.
rev. 1.00 106 ?a??? 1?? ?01? rev. 1.00 107 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom compact type tm operating modes the compact type tm can operate in one of three operating modes, compare match output mode, pwm mode or timer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both tnaf and tnpf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the tnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when an tnaf interrupt request flag is generated after a compare match occurs from comparator a. the tnpf interrupt request flag, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
rev. 1.00 108 ?a??? 1?? ?01? rev. 1.00 10? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom counte? value 0 x ? ff ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf t? o / p pin time ccrp = 0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed by ccrp value pause resume stop counte? resta?t tncclr = 0 ; tn? [ 1 : 0 ] = 00 output pin set to initial level low if tnoc = 0 output toggle wit? tnaf flag note tnio [ 1 : 0 ] = 10 a?tive hig? output sele?t he?e tnio [ 1 : 0 ] = 11 toggle output sele?t output not affe?ted by tnaf flag . remains hig? until ?eset by tnon bit output pin reset to initial value output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnpol is ?ig? compare match output mode C tncclr=0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. n=0
rev. 1.00 108 ?a??? 1?? ?01? rev. 1.00 10? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom counte? value 0 x ? ff ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf t? o / p pin time ccra = 0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed by ccra value pause resume stop counte? resta?t tncclr = 1 ; tn? [ 1 : 0 ] = 00 output pin set to initial level low if tnoc = 0 output toggle wit? tnaf flag note tnio [ 1 : 0 ] = 10 a?tive hig? output sele?t he?e tnio [ 1 : 0 ] = 11 toggle output sele?t output not affe?ted by tnaf flag . remains hig? until ?eset by tnon bit output pin reset to initial value output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnpol is ?ig? tnpf not gene?ated no tnaf flag gene?ated on ccra ove?flow output does not ??ange compare match output mode C tncclr=1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1 5. n=0
rev. 1.00 110 ?a??? 1?? ?01? rev. 1.00 111 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the tncclr bit has no effect on the pwm operation. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ctm, pwm mode, edge-aligned mode, t0dpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe?iod 1?8 ?56 ?84 51? 640 768 8?6 10?4 duty ccra if f sys =16mhz, tm clock source is f sys /4, ccrp=100b and ccra=128, the ctm pwm output frequency=(f sys /4)/512=f sys /2048=7.8125khz, duty=128/512=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ctm, pwm mode, edge-aligned mode, t0dpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe?iod ccra duty 1?8 ?56 ?84 51? 640 768 8?6 10?4 the pwm output period is determined by the ccra register value together with the tm clock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.00 110 ?a??? 1?? ?01? rev. 1.00 111 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom counte? value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf t? o / p pin ( tnoc = 1 ) time counte? ?lea?ed by ccrp pause resume counte? stop if tnon bit low counte? reset w?en tnon ?etu?ns ?ig? tndpx = 0 ; tn? [ 1 : 0 ] = 10 pw? duty cy?le set by ccra pw? ?esumes ope?ation output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnpol = 1 pw? pe?iod set by ccrp t? o / p pin ( tnoc = 0 ) pwm mode C tndpx=0 note: 1. here tndpx=0 -- counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=0
rev. 1.00 11 ? ?a??? 1?? ?01? rev. 1.00 11 ? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom counte? value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf t? o / p pin ( tnoc = 1 ) time counte? ?lea?ed by ccra pause resume counte? stop if tnon bit low counte? reset w?en tnon ?etu?ns ?ig? tndpx = 1 ; tn? [ 1 : 0 ] = 10 pw? duty cy?le set by ccrp pw? ?esumes ope?ation output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnpol = 1 pw? pe?iod set by ccra t? o / p pin ( tnoc = 0 ) pwm mode C tndpx=1 note: 1. here tndpx=1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=0
rev. 1.00 11 ? ?a??? 1?? ?01? rev. 1.00 11 ? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom standard type tm C stm the standard type tm contains five operating modes, which are compare match output, timer/event counter, capture input, single pulse output and pwm output modes. the standard tm can also be controlled with an external input pin and can drive one or two external output pins. device tm type tm name. tm input pin tm output pin ht6?f?0a 10-bit st? t?1 tck1 tp1_0? tp1_1 ht6?f40a 10-bit st? t?? tck? tp?_0? tp?_1 ht6?f50a 16-bit st? t?? tck? tp?_0? tp?_1 standard tm operation there are two sizes of standard tms, one is 10-bits wide and the other is 16-bits wide. at the core is a 10 or 16-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp comparator is 3 or 8-bits wide whose value is compared the with highest 3 or 8 bits in the counter while the ccra is the ten or sixteen bits and therefore compares all counter bits. the only way of changing the value of the 10 or 16-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the standard type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
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rev. 1.00 114 ?a??? 1?? ?01? rev. 1.00 115 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom standard type tm register description overall operation of the standard tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10 or 16-bit value, while a read/write register pair exists to store the internal 10 or 16-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three or eight ccrp bits. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t?1c0 t1pau t1ck? t1ck1 t1ck0 t1on t1rp? t1rp1 t1rp0 t?1c1 t1?1 t1?0 t1io1 t1io0 t1oc t1pol t1dpx t1cclr t?1dl d7 d6 d5 d4 d? d? d1 d0 t?1dh d? d8 t?1al d7 d6 d5 d4 d? d? d1 d0 t?1ah d? d8 10-bit standard tm register list C ht69f30a name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t??c0 t? pau t?ck? t?ck1 t?ck0 t?on t?rp? t?rp1 t?rp0 t??c1 t??1 t??0 t?io1 t?io0 t?oc t?pol t?dpx t?cclr t??dl d7 d6 d5 d4 d? d? d1 d0 t??dh d? d8 t??al d7 d6 d5 d4 d? d? d1 d0 t??ah d? d8 10-bit standard tm register list C ht69f40a name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t??c0 t? pau t?ck? t?ck1 t?ck0 t?on t??c1 t??1 t??0 t?io1 t?io0 t?oc t?pol t?dpx t?cclr t??dl d7 d6 d5 d4 d? d? d1 d0 t??dh d15 d14 d1? d1? d11 d10 d? d8 t??al d7 d6 d5 d4 d? d? d1 d0 t??ah d15 d14 d1? d1? d11 d10 d? d8 t??rp d7 d6 d5 d4 d? d? d1 d0 16-bit standard tm register list C HT69F50A
rev. 1.00 114 ?a??? 1?? ?01? rev. 1.00 115 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom 10-bit stm register defnitions C n=1 for ht69f30a and n=2 for ht69f40a ? tmnc0 register bit 7 6 5 4 3 2 1 0 name tnpau tnck? tnck1 tnck0 tnon tnrp? tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tnpau: tmn counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2, tnck1, tnck0: select tmn counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f sub 101: reserved 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tmn. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f sub are other internal clocks, the details of which can be found in the oscillator section. bit 3 tnon: tmn counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high. bit 2~0 tnrp2~tnrp0: tmn ccrp 3-bit register, compared with the tmn counter bit 9~bit 7 comparator p match period 000: 1024 tmn clocks 001: 128 tmn clocks 010: 256 tmn clocks 011: 384 tmn clocks 100: 512 tmn clocks 101: 640 tmn clocks 110: 768 tmn clocks 111: 896 tmn clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counters highest three bits. the result of this comparison can be selected to clear the internal counter if the tncclr bit is set to zero. setting the tncclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.
rev. 1.00 116 ?a??? 1?? ?01? rev. 1.00 117 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ? tmnc1 register - 10-bit stm bit 7 6 5 4 3 2 1 0 name tn?1 tn?0 tnio1 tnio0 tnoc tnpol tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 tnm1~tnm0: select tmn operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the tnm1 and tnm0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 tnio1~tnio0: select tpn_0, tpn_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tpn_0, tpn_1 01: input capture at falling edge of tpn_0, tpn_1 10: input capture at falling/rising edge of tpn_0, tpn_1 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit in the tmnc1 register. note that the output level requested by the tnio1 and tnio0 bits must be different from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to only change the values of the tnio1 and tnio0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the tnio1 and tnio0 bits are changed when the tm is running.
rev. 1.00 116 ?a??? 1?? ?01? rev. 1.00 117 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom bit 3 tnoc: tpn_0, tpn_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 tnpol: tpn_0, tpn_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn_0 or tpn_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 tndpx: tmn pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 tncclr: select tmn counter clear condition 0: tmn comparator p match 1: tmn comparator a match this bit is used to select the method which clears the counter. remember that the standard tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm, single pulse or input capture mode.
rev. 1.00 118 ?a??? 1?? ?01? rev. 1.00 11 ? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ? tmndl register C 10-bit stm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tmndl: tmn counter low byte register bit 7~bit 0 tmn 10-bit counter bit 7~bit 0 ? tmndh register C 10-bit stm bit 7 6 5 4 3 2 1 0 name d? d8 r/w r r por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tmndh: tmn counter high byte register bit 1~bit 0 tmn 10-bit counter bit 9~bit 8 ? tmnal register C 10-bit stm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tmnal: tmn ccra low byte register bit 7~bit 0 tmn 10-bit ccra bit 7~bit 0 ? tmnah register C 10-bit stm bit 7 6 5 4 3 2 1 0 name d? d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tmnah: tmn ccra high byte register bit 1~bit 0 tm1 10-bit ccra bit 9~bit 8
rev. 1.00 118 ?a??? 1?? ?01? rev. 1.00 11 ? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom 16-bit stm register defnitions C HT69F50A ? tm2c0 register bit 7 6 5 4 3 2 1 0 name t? pau t?ck? t?ck1 t?ck0 t?on r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 t2pau: tm2 counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t2ck2, t2ck1, t2ck0: select tm2 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f sub 101: reserved 110: tck2 rising edge clock 111: tck2 falling edge clock these three bits are used to select the clock source for the tm2. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f sub are other internal clocks, the details of which can be found in the oscillator section. bit 3 t2on: tm2 counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t2oc bit, when the t2on bit changes from low to high. bit 2~0 unimplemented, read as 0
rev. 1.00 1?0 ?a??? 1?? ?01? rev. 1.00 1?1 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ? tm2c1 register C 16-bit stm bit 7 6 5 4 3 2 1 0 name t??1 t??0 t?io1 t?io0 t?oc t?pol t?dpx t?cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t2m1~t2m0: select tm2 operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t2m1 and t2m0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t2io1~t2io0: select tp2_0, tp2_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp2_0, tp2_1 01: input capture at falling edge of tp2_0, tp2_1 10: input capture at falling/rising edge of tp2_0, tp2_1 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t2io1 and t2io0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t2oc bit in the tm2c1 register. note that the output level requested by the t2io1 and t2io0 bits must be different from the initial value setup using the t2oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t2on bit from low to high. in the pwm mode, the t2io1 and t2io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to only change the values of the t2io1 and t2io0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t2io1 and t2io0 bits are changed when the tm is running.
rev. 1.00 1?0 ?a??? 1?? ?01? rev. 1.00 1?1 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom bit 3 t2oc: tp2_0, tp2_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t2pol: tp2_0, tp2_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp2_0 or tp2_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t2dpx: tm2 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t2cclr: select tm2 counter clear condition 0: tm2 comparator p match 1: tm2 comparator a match this bit is used to select the method which clears the counter. remember that the standard tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the t2cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the pwm, single pulse or input capture mode.
rev. 1.00 1?? ?a??? 1?? ?01? rev. 1.00 1?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ? tm2dl register C 16-bit stm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm2dl: tm2 counter low byte register bit 7~bit 0 tm2 16-bit counter bit 7~bit 0 ? tm2dh register C 16-bit stm bit 7 6 5 4 3 2 1 0 name d15 d14 d1? d1? d11 d10 d? d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm2dh: tm2 counter high byte register bit 7~bit 0 tm2 16-bit counter bit 15~bit 8 ? tm2al register C 16-bit stm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm2al: tm2 ccra low byte register bit 7~bit 0 tm2 16-bit ccra bit 7~bit 0 ? tm2ah register C 16-bit stm bit 7 6 5 4 3 2 1 0 name d15 d14 d1? d1? d11 d10 d? d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm2ah: tm2 ccra high byte register bit 7~bit 0 tm2 16-bit ccra bit 15~bit 8 ? tm2rp register C 16-bit stm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm2rp: tm2 ccrp register bit 7~bit 0 tm2 ccrp 8-bit register, compared with the tm2 counter bit 15~bit 8. comparator p match period 0: 65536 tm2 clocks 1~255: 256(1~255) tm2 clocks these eight bits are used to setup the value on the internal ccrp 8-bit register, which are then compared with the internal counters highest eight bits. the result of this comparison can be selected to clear the internal counter if the t2cclr bit is set to zero. setting the t2cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value.
rev. 1.00 1?? ?a??? 1?? ?01? rev. 1.00 1?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom standard type tm operating modes the standard type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both tnaf and tnpf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. in the compare match output mode, the ccra can not be set to "0". as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when an tnaf interrupt request fag is generated after a compare match occurs from comparator a. the tnpf interrupt request fag, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
rev. 1.00 1?4 ?a??? 1?? ?01? rev. 1.00 1?5 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ccra ccrp 0x?ff/ 0xffff counte? ove?flow ccra int. flag tnaf ccrp int. flag tnpf ccrp > 0 counte? ?lea?ed by ccrp value t? o/p pin tnon bit pause counte? reset output pin set to initial level low if tnoc = 0 output toggle wit? tnaf flag he?e tnio1? tnio0 = 11 toggle output sele?t now tnio1? tnio0 = 10 a?tive hig? output sele?t output not affe?ted by tnaf flag. remains hig? until ?eset by tnon bit tncclr = 0; tn?[1:0] = 00 tnpau bit resume stop time ccrp > 0 ccrp = 0 tnpol bit output pin reset to initial value output inve?ts w?en tnpol is ?ig? output ?ont?olled by ot?e? pin-s?a?ed fun?tion counte? value compare match output mode C tncclr=0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. n=1 for ht69f30a; n=2 for ht69f40a/HT69F50A
rev. 1.00 1?4 ?a??? 1?? ?01? rev. 1.00 1?5 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ccrp ccra 0x?ff/ 0xffff ccra = 0 counte? ove?flows ccrp int. flag tnpf ccra int. flag tnaf ccra > 0 counte? ?lea?ed by ccra value t? o/p pin tnon bit pause counte? reset output pin reset to initial value output pin set to initial level low if tnoc = 0 output toggle wit? tnaf flag he?e tnio1? tnio0 = 11 toggle output sele?t now tnio1? tnio0 = 10 a?tive hig? output sele?t tnpau bit resume stop time tnpf not gene?ated no tnaf flag gene?ated on ccra ove?flow output does not ??ange ccra = 0 output inve?ts w?en tnpol is ?ig? tnpol bit tncclr = 1; tn?[1:0] = 00 output ?ont?olled by ot?e? pin-s?a?ed fun?tion output not affe?ted by tnaf flag ?emains hig? until ?eset by tnon bit counte? value compare match output mode C tncclr=1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. a tnpf fag is not generated when tncclr=1 5. n=1 for ht69f30a; n=2 for ht69f40a/HT69F50A
rev. 1.00 1?6 ?a??? 1?? ?01? rev. 1.00 1?7 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively and also the tnio1 and tnio0 bits should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the tncclr bit has no effect as the pwm period. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform.
rev. 1.00 1?6 ?a??? 1?? ?01? rev. 1.00 1?7 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom 10-bit stm, pwm mode, edge-aligned mode, tndpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe?iod 1?8 ?56 ?84 51? 640 768 8?6 10?4 duty ccra if f sys =16mhz, tm clock source select f sys /4, ccrp=100b and ccra=128, the stm pwm output frequency=(f sys /4)/512=f sys /2048=7.8125khz, duty=128/512=25% if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. 10-bit stm, pwm mode, edge-aligned mode, tndpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe?iod ccra duty 1?8 ?56 ?84 51? 640 768 8?6 10?4 the pwm output period is determined by the ccra register value together with the tm clock while the pwm duty cycle is defned by the ccrp register value. 16-bit stm, pwm mode, edge-aligned mode, tndpx=0 ccrp 1~255 000b pe?iod ccrp?56 655?6 duty ccra if f sys =16mhz, tm clock source select f sys /4, ccrp=2 and ccra=128, the stm pwm output frequency=(f sys /4)/(2256)=f sys /2048=7.8125khz, duty=128/(2256)=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. 16-bit stm, pwm mode, edge-aligned mode, tndpx=1 ccrp 1~255 000b pe?iod ccra duty ccrp?56 655?6 the pwm output period is determined by the ccra register value together with the tm clock while the pwm duty cycle is defned by the (ccrp256) except when the ccrp value is equal to 000b.
rev. 1.00 1?8 ?a??? 1?? ?01? rev. 1.00 1?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom counte? value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf t? o / p pin ( tnoc = 1 ) time counte? ?lea?ed by ccrp pause resume counte? stop if tnon bit low counte? reset w?en tnon ?etu?ns ?ig? tndpx = 0 ; tn? [ 1 : 0 ] = 10 pw? duty cy?le set by ccra pw? ?esumes ope?ation output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnpol = 1 pw? pe?iod set by ccrp t? o / p pin ( tnoc = 0 ) pwm mode C tndpx=0 note: 1. here tndpx=0, counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=1 for ht69f30a; n=2 for ht69f40a/HT69F50A
rev. 1.00 1?8 ?a??? 1?? ?01? rev. 1.00 1?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom counte? value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf t? o / p pin ( tnoc = 1 ) time counte? ?lea?ed by ccra pause resume counte? stop if tnon bit low counte? reset w?en tnon ?etu?ns ?ig? tndpx = 1 ; tn? [ 1 : 0 ] = 10 pw? duty cy?le set by ccrp pw? ?esumes ope?ation output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnpol = 1 pw? pe?iod set by ccra t? o / p pin ( tnoc = 0 ) pwm mode C tndpx=1 note: 1. here tndpx=1 -- counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=1 for ht69f30a; n=2 for ht69f40a/HT69F50A
rev. 1.00 1?0 ?a??? 1?? ?01? rev. 1.00 1?1 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom single pulse mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively and also the tnio1 and tnio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output leading edge is a low to high transition of the tnon bit, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a tm interrupt. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr and tndpx bits are not used in this mode.

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rev. 1.00 1?0 ?a??? 1?? ?01? rev. 1.00 1?1 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom counte? value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf t? o / p pin ( tnoc = 1 ) time counte? stopped by ccra pause resume counte? stops by softwa?e counte? reset w?en tnon ?etu?ns ?ig? tn? [ 1 : 0 ] = 10 ; tnio [ 1 : 0 ] = 11 pulse widt? set by ccra output inve?ts w?en tnpol = 1 no ccrp inte??upts gene?ated t? o / p pin ( tnoc = 0 ) tckn pin softwa?e t?igge? clea?ed by ccra mat?? tckn pin t?igge? auto . set by tckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high 5. in the single pulse mode, tnio [1:0] must be set to 11 and can not be changed 6. n=1 for ht69f30a; n=2 for ht69f40a/HT69F50A
rev. 1.00 1?? ?a??? 1?? ?01? rev. 1.00 1?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom capture input mode to select this mode bits tnm1 and tnm0 in the tmnc1 register should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tpn_0 or tpn_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnio1 and tnio0 bits in the tmnc1 register. the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpn_0 or tpn_1 pin the present value in the counter will be latched into the ccra registers and a tm interrupt generated. irrespective of what events occur on the tpn_0 or tpn_1 pin the counter will continue to free run until the tnon bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tm interrupt will also be generated. counting the number of overflow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the tnio1 and tnio0 bits can select the active trigger edge on the tpn_0 or tpn_1 pin to be a rising edge, falling edge or both edge types. if the tnio1 and tnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpn_0 or tpn_1 pin, however it must be noted that the counter will continue to run. as the tpn_0 or tpn_1 pin is pin shared with other functions, care must be taken if the tm is in the input capture mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr and tndpx bits are not used in this mode.
rev. 1.00 1?? ?a??? 1?? ?01? rev. 1.00 1?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom counte? value yy ccrp tnon tnpau ccrp int . flag tnpf ccra int . flag tnaf ccra value time counte? ?lea?ed by ccrp pause resume counte? reset tn? [ 1 : 0 ] = 01 t? ?aptu?e pin tpn _ x xx counte? stop tnio [ 1 : 0 ] value xx yy xx yy a?tive edge a?tive edge a?tive edge 00 C rising edge 01 C falling edge 10 C bot? edges 11 C disable captu?e capture input mode note: 1. tnm [1:0]=01 and active edge set by the tnio [1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function -- tnoc and tnpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero 6. n=1 for ht69f30a; n=2 for ht69f40a/HT69F50A
rev. 1.00 1?4 ?a??? 1?? ?01? rev. 1.00 1?5 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom enhanced type tm C etm the enhanced type tm contains five operating modes, which are compare match output, timer/event counter, capture input, single pulse output and pwm output modes. the enhanced tm can also be controlled with an external input pin and can drive three or four external output pins. device tm type tm name. tm input pin tm output pin ht6?f?0a ht6? f40a ht6?f50a 10-bit et? t?1 tck1 tp1a; tp1b_0? tp1b_1? tp1b_?? enhanced tm operation at its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal or external clock source. there are three internal comparators with the names, comparator a, comparator b and comparator p. these comparators will compare the value in the counter with the ccra, ccrb and ccrp registers. the ccrp comparator is 3-bits wide whose value is compared with the highest 3-bits in the counter while ccra and ccrb are 10-bits wide and therefore compared with all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the enhanced type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control output pins. all operating setup conditions are selected using relevant internal registers.
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rev. 1.00 1?4 ?a??? 1?? ?01? rev. 1.00 1?5 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom enhanced type tm register description overall operation of the enhanced tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrb value. the remaining three registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t?1c0 t1pau t1ck? t1ck1 t1ck0 t1on t1rp? t1rp1 t1rp0 t?1c1 t1a?1 t1a?0 t1aio1 t1aio0 t1aoc t1apol t1cdn t1cclr t?1c? t1b?1 t1b?0 t1bio1 t1bio0 t1boc t1bpol t1pw?1 t1pw?0 t?1dl d7 d6 d5 d4 d? d? d1 d0 t?1dh d? d8 t?1al d7 d6 d5 d4 d? d? d1 d0 t?1ah d? d8 t?1bl d7 d6 d5 d4 d? d? d1 d0 t?1bh d? d8 10-bit enhanced tm register list tm1c0 register C 10-bit etm bit 7 6 5 4 3 2 1 0 name t1pau t1ck? t1ck1 t1ck0 t1on t1rp? t1rp1 t1rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t1pau: tm1 counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t1ck2~t1ck0: select tm1 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f sub 101: reserved 110: tck1 rising edge clock 111: tck1 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f sub are other internal clocks, the details of which can be found in the oscillator section.
rev. 1.00 1?6 ?a??? 1?? ?01? rev. 1.00 1?7 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom bit 3 t1on: tm1 counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t1oc bit, when the t1on bit changes from low to high. bit 2~0 t1rp2~t1rp0: tm1 ccrp 3-bit register, compared with the tm1 counter bit 9~bit 7 comparator p match period 000: 1024 tm1 clocks 001: 128 tm1 clocks 010: 256 tm1 clocks 011: 384 tm1 clocks 100: 512 tm1 clocks 101: 640 tm1 clocks 110: 768 tm1 clocks 111: 896 tm1 clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counter highest three bits. the result of this comparison can be selected to clear the internal counter if the t1cclr bit is set to zero. setting the t1cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.
rev. 1.00 1?6 ?a??? 1?? ?01? rev. 1.00 1?7 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom tm1c1 register C 10-bit etm bit 7 6 5 4 3 2 1 0 name t1a?1 t1a?0 t1aio1 t1aio0 t1aoc t1apol t1cdn t1cclr r/w r/w r/w r/w r/w r/w r/w r r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1am1~t1am0: select tm1 ccra operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t1am1 and t1am0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t1aio1~t1aio0: select tp1a output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1a 01: input capture at falling edge of tp1a 10: input capture at falling/rising edge of tp1a 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1aio1 and t1aio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1aoc bit in the tm1c1 register. note that the output level requested by the t1aio1 and t1aio0 bits must be different from the initial value setup using the t1aoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1aio1 and t1aio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the t1aio1 and t1aio0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t1aio1 and t1aio0 bits are changed when the tm is running.
rev. 1.00 1?8 ?a??? 1?? ?01? rev. 1.00 1?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom bit 3 t1aoc: tp1a output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1apol: tp1a output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1a output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t1cdn: tm1 counter count up or down fag 0: count up 1: count down bit 0 t1cclr: select tm1 counter clear condition 0: tm1 comparator p match 1: tm1 comparator a match this bit is used to select the method which clears the counter. remember that the enhanced tm contains three comparators, comparator a, comparator b and comparator p, but only comparator a or comparator p can be selected to clear the internal counter. with the t1cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the single pulse or input capture mode.
rev. 1.00 1?8 ?a??? 1?? ?01? rev. 1.00 1?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom tm1c2 register C 10-bit etm bit 7 6 5 4 3 2 1 0 name t1b?1 t1b?0 t1bio1 t1bio0 t1boc t1bpol t1pw?1 t1pw?0 r/w r/w r/w r/w r/w r/w r/w r r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1bm1~t1bm0: select tm1 ccrb operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t1bm1 and t1bm0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t1bio1~t1bio0: select tp1b_0, tp1b_1, tp1b_2 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1b_0, tp1b_1, tp1b_2 01: input capture at falling edge of tp1b_0, tp1b_1, tp1b_2 10: input capture at falling/rising edge of tp1b_0, tp1b_1, tp1b_2 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1bio1 and t1bio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1boc bit in the tm1c2 register. note that the output level requested by the t1bio1 and t1bio0 bits must be different from the initial value setup using the t1boc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1bio1 and t1bio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to only change the value of the t1bio1 and t1bio0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t1bio1 and t1bio0 bits are changed when the tm is running.
rev. 1.00 140 ?a??? 1?? ?01? rev. 1.00 141 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom bit 3 t1boc: tp1b_0, tp1b_1, tp1b_2 output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1bpol: tp1b_0, tp1b_1, tb1b_2 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1b_0, tp1b_1, tp1b_2 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1~0 t1pwm1~t1pwm0: select pwm mode 00: edge aligned 01: centre aligned, compare match on count up 10: centre aligned, compare match on count down 11: centre aligned, compare match on count up or down tm1dl register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm1dl: tm1 counter low byte register bit 7~bit 0 tm1 10-bit counter bit 7~bit 0 tm1dh register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d? d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm1dh: tm1 counter high byte register bit 1~bit 0 tm1 10-bit counter bit 9~bit 8
rev. 1.00 140 ?a??? 1?? ?01? rev. 1.00 141 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom tm1al register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1al: tm1 ccra low byte register bit 7~bit 0 tm1 10-bit ccra bit 7~bit 0 tm1ah register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d? d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm1ah: tm1 ccra high byte register bit 1~bit 0 tm1 10-bit ccra bit 9~bit 8 tm1bl register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1bl: tm1 ccrb low byte register bit 7~bit 0 tm1 10-bit ccrb bit 7~bit 0 tm1bh register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d? d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm1bh: tm1 ccrb high byte register bit 1~bit 0 tm1 10-bit ccrb bit 9~bit 8
rev. 1.00 14? ?a??? 1?? ?01? rev. 1.00 14? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom enhanced type tm operating modes the enhanced type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the tnam1 and tnam0 bits in the tmnc1, and the tnbm1 and tnbm0 bits in the tmnc2 register. etm operating mode ccra compare match output mode ccra timer/ counter mode ccra pwm output mode ccra single pulse output mode ccra input capture mode ccrb compa?e ?at?? output ?ode ccrb time ?/counte? ?ode ccrb pw? output ?ode ccrb single pulse output ?ode ccrb input captu?e ?ode ?: permitted; : not permitt compare output mode to select this mode, bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1/tmnc2 registers should be all cleared to zero. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both the tnaf and tnpf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when an tnaf or tnbf interrupt request fag is generated after a compare match occurs from comparator a or comparator b. the tnpf interrupt request flag, generated from a compare match from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state is determined by the condition of the tnaio1 and tnaio0 bits in the tmnc1 register for etm ccra, and the tnbio1 and tnbio0 bits in the tmnc2 register for etm ccrb. the tm output pin can be selected using the tnaio1, tnaio0 bits (for the tpna pin) and tnbio1, tnbio0 bits (for the tpnb_0, tpnb_1 or tpnb_2 pins) to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a or a compare match occurs from comparator b. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnaoc or tnboc bit for tpna or tpnb_0, tpnb_1, tpnb_2 output pins. note that if the tnaio1,tnaio0 and tnbio1, tnbio0 bits are zero then no pin change will take place.
rev. 1.00 14? ?a??? 1?? ?01? rev. 1.00 14? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom counte? value 0 x ? ff ccrp ccra tnon tnpau tnapol ccrp int . flag tnpf ccra int . flag tnaf tpna o / p pin time ccrp = 0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed by ccrp value pause resume stop counte? resta?t tncclr = 0 ; tna? [ 1 : 0 ] = 00 output pin set to initial level low if tnaoc = 0 output toggle wit? tnaf flag note tnaio [ 1 : 0 ] = 10 a?tive hig? output sele?t he?e tnaio [ 1 : 0 ] = 11 toggle output sele?t output not affe?ted by tnaf flag . remains hig? until ?eset by tnon bit output pin reset to initial value output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnapol is ?ig? etm ccra compare match output mode C tncclr=0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tpna output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. n=1 for ht69f40a/HT69F50A
rev. 1.00 144 ?a??? 1?? ?01? rev. 1.00 145 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom counte? value 0 x ? ff ccrp ccrb tnon tnpau tnbpol ccrp int . flag tnpf ccrb int . flag tnbf tpnb o / p pin time ccrp = 0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed by ccrp value pause resume stop counte? resta?t tncclr = 0 ; tnb? [ 1 : 0 ] = 00 output pin set to initial level low if tnboc = 0 output toggle wit? tnbf flag note tnbio [ 1 : 0 ] = 10 a?tive hig? output sele?t he?e tnbio [ 1 : 0 ] = 11 toggle output sele?t output not affe?ted by tnbf flag . remains hig? until ?eset by tnon bit output pin reset to initial value output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnbpol is ?ig? etm ccrb compare match output mode C tncclr=0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tpnb output pin is controlled only by the tnbf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. n=1 for ht69f40a/HT69F50A
rev. 1.00 144 ?a??? 1?? ?01? rev. 1.00 145 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom counte? value 0 x ? ff ccrp ccra tnon tnpau tnapol ccrp int . flag tnpf ccra int . flag tnaf tpna o / p pin time ccra = 0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed by ccra value pause resume stop counte? resta?t tncclr = 1 ; tna? [ 1 : 0 ] = 00 output pin set to initial level low if tnaoc = 0 output toggle wit? tnaf flag note tnaio [ 1 : 0 ] = 10 a?tive hig? output sele?t he?e tnaio [ 1 : 0 ] = 11 toggle output sele?t output not affe?ted by tnaf flag . remains hig? until ?eset by tnon bit output pin reset to initial value output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnapol is ?ig? tnpf not gene?ated no tnaf flag gene?ated on ccra ove?flow output does not ??ange etm ccra compare match output mode C tncclr=1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tpna output pin is controlled only by the tnaf fag 3. the tpna output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1 5. n=1 for ht69f40a/HT69F50A
rev. 1.00 146 ?a??? 1?? ?01? rev. 1.00 147 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom counte? value 0 x ? ff ccrb ccra tnon tnpau tnbpol ccrb int . flag tnbf ccra int . flag tnaf tpnb o / p pin time ccra = 0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed by ccra value pause resume stop counte? resta?t tncclr = 1 ; tnb? [ 1 : 0 ] = 00 output pin set to initial level low if tnboc = 0 output toggle wit? tnbf flag note tnbio [ 1 : 0 ] = 10 a?tive hig? output sele?t he?e tnbio [ 1 : 0 ] = 11 toggle output sele?t output not affe?ted by tnbf flag . remains hig? until ?eset by tnon bit output pin reset to initial value output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnbpol is ?ig? no tnaf flag gene?ated on ccra ove?flow etm ccrb compare match output mode C tncclr=1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tpnb output pin is controlled only by the tnbf fag 3. the tpnb output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1 5. n=1 for ht69f40a/HT69F50A
rev. 1.00 146 ?a??? 1?? ?01? rev. 1.00 147 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom timer/counter mode to select this mode, bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1 and tmnc2 registers should all be set high. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared functions. pwm output mode to select this mode, the required bit pairs, tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1 and tmnc2 registers should be set to 10 respectively and also the tnaio1, tnaio0 and tnbio1, tnbio0 bits should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely fexible. in the pwm mode, the tncclr bit is used to determine in which way the pwm period is controlled. with the tncclr bit set high, the pwm period can be fnely controlled using the ccra registers. in this case the ccrb registers are used to set the pwm duty value (for tpnb_x output pins). the ccrp bits are not used and tpna output pin is not used. the pwm output can only be generated on the tpnb_x output pins. with the tncclr bit cleared to zero, the pwm period is set using one of the eight values of the three ccrp bits, in multiples of 128. now both ccra and ccrb registers can be used to setup different duty cycle values to provide dual pwm outputs on their relative tpna and tpnb_x pins. the tnpwm1 and tnpwm0 bits determine the pwm alignment type, which can be either edge or centre type. in edge alignment, the leading edge of the pwm signals will all be generated concurrently when the counter is reset to zero. with all power currents switching on at the same time, this may give rise to problems in higher power applications. in centre alignment the centre of the pwm active signals will occur sequentially, thus reducing the level of simultaneous power switching currents. interrupt fags, one for each of the ccra, ccrb and ccrp, will be generated when a compare match occurs from the comparator a, comparator b or comparator p. the tnaoc and tnboc bits in the tmnc1 and tmnc2 register are used to select the required polarity of the pwm waveform while the two tnaio1, tnaio0 and tnbio1, tnbio0 bits pairs are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnapol and tnbpol bit are used to reverse the polarity of the pwm output waveform.
rev. 1.00 148 ?a??? 1?? ?01? rev. 1.00 14? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom etm, pwm mode, edge-aligned mode, tncclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe?iod 1?8 ?56 ?84 51? 640 768 8?6 10?4 a duty ccra b duty ccrb if f sys =12mhz, tm clock source select f sys /4, ccrp=100b, ccra=128 and ccrb=256, the tpna pwm output frequency=(f sys /4)/512=f sys /2048=5.8594khz, duty=128/512=25%. the tpnb_x pwm output frequency=(f sys /4)/512=f sys /2048=5.8594khz, duty=256/512=50%. if the duty value defned by ccra or ccrb register is equal to or greater than the period value, then the pwm output duty is 100%. etm, pwm mode, edge-aligned mode, tncclr=1 ccra 1 2 3 511 512 1021 1022 1023 pe?iod 1 ? ? 511 51? 10?1 10?? 10?? b duty ccrb etm, pwm mode, center-aligned mode, tncclr=0 ccra 001b 010b 011b 100b 101b 110b 111b 000b pe?iod ?56 51? 768 10?4 1?80 15?6 17?? ?046 a duty (ccra?)-1 b duty (ccrb?)-1 etm, pwm mode, center-aligned mode, tncclr=1 ccra 1 2 3 511 512 1021 1022 1023 pe?iod ? 4 6 10?? 10?4 ?04? ?044 ?046 b duty (ccrb?)-1
rev. 1.00 148 ?a??? 1?? ?01? rev. 1.00 14? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom counte? value ccrp ccra tnon tnpau tnapol ccra int . flag tnaf ccrb int . flag tnbf tpna pin ( tnaoc = 1 ) time counte? clea?ed by ccrp pause resume stop counte? resta?t tncclr = 0 ; tna? [ 1 : 0 ] = 10? tnb? [ 1 : 0 ] = 10; tnpw? [ 1 : 0 ] = 00 output pin reset to initial value output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnapol is ?ig? ccrb ccrp int . flag tnpf tpnb pin ( tnboc = 1 ) tpnb pin ( tnboc = 0 ) duty cy?le set by ccra duty cy?le set by ccrb pw? pe?iod set by ccrp duty cy?le set by ccra duty cy?le set by ccra etm pwm mode C edge aligned note: 1. here tncclr=0 therefore ccrp clears the counter and determines the pwm period 2. the internal pwm function continues running even when tnaio [1:0] (or tnbio [1:0])=00 or 01 3. ccra controls the tpna pwm duty and ccrb controls the tpnb pwm duty 4. n=1 for ht69f40a/HT69F50A
rev. 1.00 150 ?a??? 1?? ?01? rev. 1.00 151 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom counte? value ccra tnon tnpau tnbpol ccrb int . flag tnbf time counte? clea?ed by ccra pause resume stop counte? resta?t tncclr = 1 ; tnb? [ 1 : 0 ] = 10; tnpw? [ 1 : 0 ] = 00 output pin reset to initial value output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnbpol is ?ig? ccrb ccrp int . flag tnpf tpnb pin ( tnboc = 1 ) tpnb pin ( tnboc = 0 ) duty cy?le set by ccrb pw? pe?iod set by ccra etm pwm mode C edge aligned note: 1. here tncclr=1 therefore ccra clears the counter and determines the pwm period 2. the internal pwm function continues running even when tnbio [1:0]=00 or 01 3. the ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 4. here the tm pin control register should not enable the tpna pin as a tm output pin. 5. n=1 for ht69f40a/HT69F50A
rev. 1.00 150 ?a??? 1?? ?01? rev. 1.00 151 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom counte? value ccrp ccra tnon tnpau tnapol ccra int . flag tnaf ccrb int . flag tnbf tpna pin ( tnaoc = 1 ) time pause resume stop counte? resta?t tncclr = 0 ; tna? [ 1 : 0 ] = 10? tnb? [ 1 : 0 ] = 10; tnpw? [ 1 : 0 ] = 11 output pin reset to initial value output ?ont?olled by ot?e? pin - s?a?ed fun?tion output inve?ts w?en tnapol is ?ig? ccrb ccrp int . flag tnpf tpnb pin ( tnboc = 1 ) tpnb pin ( tnboc = 0 ) duty cy?le set by ccra duty cy?le set by ccrb pw? pe?iod set by ccrp etm pwm mode C centre aligned note: 1. here tncclr=0 therefore ccrp clears the counter and determines the pwm period 2. tnpwm [1:0]=11 therefore the pwm is centre aligned 3. the internal pwm function continues running even when tnaio [1:0] (or tnbio [1:0])=00 or 01 4. ccra controls the tpna pwm duty and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value 6. n=1 for ht69f40a/HT69F50A
rev. 1.00 15? ?a??? 1?? ?01? rev. 1.00 15? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom counte? value ccra tnon tnpau tnbpol ccra int . flag tnaf ccrb int . flag tnbf time pause resume stop counte? resta?t tncclr = 1 ; tnb? [ 1 : 0 ] = 10; tnpw? [ 1 : 0 ] = 11 output pin reset to initial value output ?ont?olled by ot?e? pin - s?a?ed fun?tion ccrb tpnb pin ( tnboc = 1 ) tpnb pin ( tnboc = 0 ) duty cy?le set by ccrb pw? pe?iod set by ccra output inve?ts w?en tnbpol is ?ig? ccrp int . flag tnpf etm pwm mode C centre aligned note: 1. here tncclr=1 therefore ccra clears the counter and determines the pwm period 2. tnpwm [1:0]=11 therefore the pwm is centre aligned 3. the internal pwm function continues running even when tnbio [1:0]=00 or 01 4. ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value 6. n=1 for ht69f40a/HT69F50A
rev. 1.00 15? ?a??? 1?? ?01? rev. 1.00 15? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom single pulse output mode to select this mode, the required bit pairs, tnam1, tnam0 and tnbm1, tnbm0 should be set to 10 respectively and also the corresponding tnaio1, tnaio0 and tnbio1, tnbio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse tpna output leading edge is a low to high transition of the tnon bit, which can be implemented using the application program. the trigger for the pulse tpnb_x output leading edge is a compare match from comparator b, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output of tpna. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge of tpna will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge of tpna and tpnb_x will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge of tpna and tpnb_x. in this way the ccra value can be used to control the pulse width of tpna. the (ccra-ccrb) value can be used to control the pulse width of tpnb_x. a compare match from comparator a and comparator b will also generate tm interrupts. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr bit is also not used. s/w command settnon o? tckn pin t?ansition ccrb leading edge ccra t?ailing edge s/w command clrtnon o? ccra compa?e ?at?? tpna output pin tpnb output pin pulse widt? = (ccra-ccrb ) value pulse widt? = ccra value counte? value ccrb ccra 0 time tnon = 1 ccrb compa?e ?at?? s/w command clrtnon o? ccra compa?e ?at?? ccrb t?ailing edge ccra leading edge tnon bit 1 0 tnon bit 1 0 tnon bit 0 1 single pulse generation
rev. 1.00 154 ?a??? 1?? ?01? rev. 1.00 155 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom counte? value ccrb ccra tnon tnpau tnapol ccrb int . flag tnbf ccra int . flag tnaf tpna pin ( tnaoc = 1 ) time counte? stopped by ccra pause resume counte? stops by softwa?e counte? reset w?en tnon ?etu?ns ?ig? tna? [1 :0 ] = 10 ? tnb? [1 :0 ] = 10 ; tnaio [1 : 0 ] = 11 ? tnbio [1 :0 ] = 11 pulse widt? set by ( ccra -ccrb ) output inve?ts w?en tnbpol = 1 tckn pin softwa?e t?igge? clea?ed by ccra mat?? tckn pin t?igge? auto . set by tckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? tnbpol tpna pin ( tnaoc = 0 ) tpnb pin ( tnboc = 1 ) tpnb pin ( tnboc = 0 ) pulse widt? set by ccra output inve?ts w?en tnapol = 1 etm C single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high 5. in the single pulse mode, tnaio [1:0] and tnbio [1:0] must be set to 11 and can not be changed 6. n=1 for ht69f40a/HT69F50A
rev. 1.00 154 ?a??? 1?? ?01? rev. 1.00 155 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom capture input mode to select this mode bits tnam 1, tnam0 and tnbm1, tnbm0 in the tmnc1 and tmnc2 registers should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tpna and tpnb_0, tpnb_1, tpnb_2 pins, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnaio1, tnaio0 and tnbio1, tnbio0 bits in the tmnc1 and tmnc2 registers. the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpna and tpnb_0, tpnb_1, tpnb_2 pins the present value in the counter will be latched into the ccra and ccrb registers and a tm interrupt generated. irrespective of what events occur on the tpna and tpnb_0, tpnb_1, tpnb_2 pins the counter will continue to free run until the tnon bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the tnaio1, tnaio0 and tnbio1, tnbio0 bits can select the active trigger edge on the tpna and tpnb_0, tpnb_1, tpnb_2 pins to be a rising edge, falling edge or both edge types. if the tnaio1, tnaio0 and tnbio1, tnbio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpna and tpnb_0, tpnb_1, tpnb_2 pins, however it must be noted that the counter will continue to run. as the tpna and tpnb_0, tpnb_1, tpnb_2 pins are pin shared with other functions, care must be taken if the tm is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr, tnaoc, tnboc, tnapol and tnbpol bits are n ot used in this mode.
rev. 1.00 156 ?a??? 1?? ?01? rev. 1.00 157 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom counte? value yy ccrp tnon tnpau ccrp int . flag tnpf ccra int . flag tnaf ccra value time counte? ?lea?ed by ccrp pause resume counte? reset tna? [ 1:0 ] = 01 t? ?aptu?e pin tpna xx counte? stop tnaio [1 :0 ] value xx yy xx yy a?tive edge a?tive edge a?tive edge 00 C rising edge 01 C falling edge 10 C bot? edges 11 C disable captu?e etm ccra capture input mode note: 1. tnam [1:0]=01 and active edge set by the tnaio [1:0] bits 2. the tm capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function -- tnaoc and tnapol bits not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero 6. n=1 for ht69f40a/HT69F50A
rev. 1.00 156 ?a??? 1?? ?01? rev. 1.00 157 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ccrp counte? ove?flow ccrp int. flag tnpf ccrb int. flag tnbf tnon bit pa use co un te? re set tnpau bit resu me sto p yy xx ccrb value xx t? captu?e pin yy tnbio1? tnbio0 value 00 - rising edge 01 - falling edge 11 - disable captu?e a?tive edge a? ti ve edge xx 10 - bot? edges a?tive edges yy tnb?1? tnb?0 = 01 tim e counte? value etm ccrb capture input mode note: 1. tnbm [1:0]=01 and active edge set by the tnbio [1:0] bits 2. the tm capture input pin active edge transfers the counter value to ccrb 3. tncclr bit not used 4. no output function -- tnboc and tnbpol bits not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero 6. n=1 for ht69f40a/HT69F50A
rev. 1.00 158 ?a??? 1?? ?01? rev. 1.00 15? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer module requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions. the external interrupts are generated by the action of the external int0~int1 pins, while the internal interrupts are generated by various internal functions such as the tms, time base and lvd. interrupt registers overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the special purpose data memory, as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. the frst is the intc0~intc1 registers which setup the primary interrupts, the second is the mfi0~mfi2 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes global e?i intn pin intne intnf n=0~1 time base tbne tbnf n=0~1 ?ulti-fun?tion ?fne ?fnf n=0~? lvd lve lvf eepro? dee def t? tnpe tnpf n=0~? tnae tnaf n=0~? tnbe tnbf n=1 interrupt register bit naming conventions
rev. 1.00 158 ?a??? 1?? ?01? rev. 1.00 15? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom interrupt register contents ? ht69f30a name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 tb0f int1f int0f tb0e int1e int0e e?i intc1 ?f?f ?f1f ?f0f tb1f ?f?e ?f1e ?f0e tb1e ?fi0 t0af t0pf t0ae t0pe ?fi1 t1af t1pf t1ae t1pe ?fi? def lvf dee lve ? ht69f40a/HT69F50A name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 tb0f int1f int0f tb0e int1e int0e e?i intc1 ?f?f ?f1f ?f0f tb1f ?f?e ?f1e ?f0e tb1e ?fi0 t?af t?pf t0af t0pf t?ae t?pe t0ae t0pe ?fi1 t1bf t1af t1pf t1be t1ae t1pe ?fi? def lvf dee lve integ register bit 7 6 5 4 3 2 1 0 name int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3~2 int1s1, int1s0: interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1, int0s0: interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edge
rev. 1.00 160 ?a??? 1?? ?01? rev. 1.00 161 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom intc0 register bit 7 6 5 4 3 2 1 0 name tb0f int1f int0f tb0e int1e int0e e?i r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 tb0f: time base 0 interrupt request fag 0: no request 1: interrupt request bit 5 int1f: int1 interrupt request fag 0: no request 1: interrupt request bit 4 int0f: int0 interrupt request fag 0: no request 1: interrupt request bit 3 tb0e: time base 0 interrupt control 0: disable 1: enable bit 2 int1e: int1 interrupt control 0: disable 1: enable bit 1 int0e: int0 interrupt control 0: disable 1: enable bit 0 emi: global interrupt control 0: disable 1: enable
rev. 1.00 160 ?a??? 1?? ?01? rev. 1.00 161 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom intc1 register bit 7 6 5 4 3 2 1 0 name ?f?f ?f1f ?f0f tb1f ?f?e ?f1e ?f0e tb1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf2f: multi-function interrupt 2 request fag 0: no request 1: interrupt request bit 6 mf1f: multi-function interrupt 1 request fag 0: no request 1: interrupt request bit 5 mf0f: multi-function interrupt 0 request fag 0: no request 1: interrupt request bit 4 tb1f: time base 1 interrupt request fag 0: no request 1: interrupt request bit 3 mf2e: multi-function interrupt 2 control 0: disable 1: enable bit 2 mf1e: multi-function interrupt 1 control 0: disable 1: enable bit 1 mf0e: multi-function interrupt 0 control 0: disable 1: enable bit 0 tb1e: time base 1 interrupt control 0: disable 1: enable mfi0 register C ht69f30a bit 7 6 5 4 3 2 1 0 name t0af t0pf t0ae t0pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t0af: tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf: tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t0ae: tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe: tm0 comparator p match interrupt control 0: disable 1: enable
rev. 1.00 16? ?a??? 1?? ?01? rev. 1.00 16? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom mfi0 register C ht69f40a/HT69F50A bit 7 6 5 4 3 2 1 0 name t?af t?pf t0af t0pf t?ae t?pe t0ae t0pe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t2af: tm2 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 t2pf: tm2 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 t0af: tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf: tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 t2ae: tm2 comparator a match interrupt control 0: disable 1: enable bit 2 t2pe: tm2 comparator p match interrupt control 0: disable 1: enable bit 1 t0ae: tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe: tm0 comparator p match interrupt control 0: disable 1: enable mfi1 register C ht69f30a bit 7 6 5 4 3 2 1 0 name t1af t1pf t1ae t1pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t1af: tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf: tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t1ae: tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe: tm1 comparator p match interrupt control 0: disable 1: enable
rev. 1.00 16? ?a??? 1?? ?01? rev. 1.00 16? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom mfi1 register C ht69f40a/HT69F50A bit 7 6 5 4 3 2 1 0 name t1bf t1af t1pf t1be t1ae t1pe r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 t1bf: tm1 comparator b match interrupt request fag 0: no request 1: interrupt request bit 5 t1af: tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf: tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as 0 bit 2 t1be: tm1 comparator b match interrupt control 0: disable 1: enable bit 1 t1ae: tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe: tm1 comparator p match interrupt control 0: disable 1: enable mfi2 register bit 7 6 5 4 3 2 1 0 name def lvf dee lve r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 def: data eeprom interrupt request fag 0: no request 1: interrupt request bit 4 lvf: lvd interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 dee: data eeprom interrupt control 0: disable 1: enable bit 0 lve: lvd interrupt control 0: disable 1: enable
rev. 1.00 164 ?a??? 1?? ?01? rev. 1.00 165 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom interrupt operation when the conditions for an interrupt event occur, such as a tm comparator p, comparator a or comparator b match etc, the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a "reti" , which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is applied. all of the interrupt request fags when set will wake-up the device if it is in sleep or idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode.
rev. 1.00 164 ?a??? 1?? ?01? rev. 1.00 165 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom int0 pin int1 pin int0f int1f int0e int1e e?i 04h e?i 08h ?. fun?t. 0 ?f0f ?f0e 0ch 10h 14h time base 0 tb0f tb0e 18h lvd lvf lve 1ch inte??upt name request flags enable bits ?aste? enable vector e?i auto disabled in isr p?io?ity hig? low t?1 p t1pf t1pe t?1 a t1af t1ae ?. fun?t. 1 ?f1f ?f1e t?0 p t0pf t0pe t?0 a t0af t0ae inte??upts ?ontained wit?in ?ulti-fun?tion inte??upts xxe enable bits xxf request flag? auto ?eset in isr legend xxf request flag? no auto ?eset in isr e?i e?i ?. fun?t. ? ?f?f ?f?e eepro? def dee e?i time base 1 tb1f tb1e e?i e?i interrupt structure C ht69f30a int0 pin int1 pin int0f int1f int0e int1e e?i 04h e?i 08h ?. fun?t. 0 ?f0f ?f0e 0ch 10h 14h time base 0 tb0f tb0e 18h lvd lvf lve 1ch inte??upt name request flags enable bits ?aste? enable vector e?i auto disabled in isr p?io?ity hig? low t?1 p t1pf t1pe t?1 a t1af t1ae ?. fun?t. 1 ?f1f ?f1e t?0 p t0pf t0pe t?0 a t0af t0ae inte??upts ?ontained wit?in ?ulti-fun?tion inte??upts xxe enable bits xxf request flag? auto ?eset in isr legend xxf request flag? no auto ?eset in isr e?i e?i ?. fun?t. ? ?f?f ?f?e eepro? def dee e?i t?? p t?pf t?pe t?? a t?af t?ae t?1 b t1bf t1be time base 1 tb1f tb1e e?i e?i interrupt structure C ht69f40a/HT69F50A
rev. 1.00 166 ?a??? 1?? ?01? rev. 1.00 167 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom external interrupt the external interrupts are controlled by signal transitions on the pins int0~int1. an external interrupt request will take place when the external interrupt request fags, int0f~int1f, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e~int1e, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. when the interrupt is serviced, the external interrupt request fags, int0f~int1f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. multi-function interrupt within this device there are up to three multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts, eeprom interrupt and lvd interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request flags, mfnf, are set. the multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. to allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi-function request fag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that, although the multi-function interrupt fags will be automatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, namely the tm interrupts, eeprom interrupt and lvd interrupt will not be automatically reset and must be manually reset by the application program.
rev. 1.00 166 ?a??? 1?? ?01? rev. 1.00 167 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom time base interrupt the function of the time base interrupt is to provide regular time signal in the form of an internal interrupt. it is controlled by the overflow signal from its internal timer. when this happens its interrupt request fag, tbnf, will be set. to allow the program to branch to its respective interrupt vector addresses, the global interrupt enable bit, emi and time base enable bit, tbne, must frst be set. when the interrupt is enabled, the stack is not full and the time base overfows, a subroutine call to its respective vector location will take place. when the interrupt is serviced, the interrupt request flag, tbnf, will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the time base interrupt is to provide an interrupt signal at fxed time periods. its clock source, f tb , originates from the internal clock source f sub or f sys /4. and then passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source which in turn controls the time base interrupt period is selected using a bit in the tbc register. tbc register bit 7 6 5 4 3 2 1 0 name tbon tbck tb11 tb10 lxtlp tb0? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 0 1 1 1 bit 7 tbon: time base 0 and time base 1 enable/disable 0: disable 1: enable bit 6 tbck: tb clock f tb select 0: f sub 1: f sys /4 bit 5~4 tb11~tb10: time base 1 time-out period selection 00: 2 12 /f tb 01: 2 13 /f tb 10: 2 14 /f tb 11: 2 15 /f tb bit 3 lxtlp: lxt low power control 0: disable (lxt quick start-up) 1: enable (lxt low power start-up) bit 2~0 tb02~tb00: time base 0 time-out period 000: 2 8 /f tb 001: 2 9 /f tb 010: 2 10 /f tb 011: 2 11 /f tb 100: 2 12 /f tb 101: 2 13 /f tb 110: 2 14 /f tb 111: 2 15 /f tb

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time base interrupt
rev. 1.00 168 ?a??? 1?? ?01? rev. 1.00 16? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom eeprom interrupt the eeprom interrupt is contained within the multi-function interrupt. an eeprom interrupt request will take place when the eeprom interrupt request fag, def, is set, which occurs when an eeprom write operation ends. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the eeprom interrupt enable bit, dee, and muti- function interrupt enable bits, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom write operation ends, a subroutine call to the respective multi-function interrupt vector, will take place.when the eeprom interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the def fag will not be automatically cleared, it has to be cleared by the application program. lvd interrupt the low voltage detector interrupt is contained within the multi-function interrupt. an lvd interrupt request will take place when the lvd interrupt request flag, lvf, is set, which occurs when the low voltage detector function detects a low power supply voltage. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, low voltage interrupt enable bit, lve, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the multi-function interrupt vector, will take place. when the low voltage interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the lvf fag will not be automatically cleared, it has to be cleared by the application program. tm interrupts the compact and standard type tms have two interrupts each, while the enhanced type tm has three interrupts. all of the tm interrupts are contained within the multi-function interrupts. for each of the compact and standard type tms there are two interrupt request fags tnpf and tnaf and two enable bits tnpe and tnae. for the enhanced type tm there are three interrupt request fags tnpf, tnaf and tnbf and three enable bits tnpe, tnae and tnbe. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p, a or b match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program.
rev. 1.00 168 ?a??? 1?? ?01? rev. 1.00 16? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom interrupt wake-up function each of the interrupt functions has the capability of waking up the microcontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function. programming considerations by disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained within a multi-function interrupt, then when the interrupt service routine is executed, as only the multi-function interrupt request fags, mf0f~mf2f, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in sleep or idle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interrupt from waking up the microcontroller then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.00 170 ?a??? 1?? ?01? rev. 1.00 171 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom low voltage detector C lvd each device has a low voltage detector function, also known as lvd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low voltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name lvdc. three bits in this register, vlvd2~vlvd0, are used to select one of eight fxed voltages below which a low voltage condition will be detemined. a low voltage condition is indicated when the lvdo bit is set. if the lvdo bit is low, this indicates that the v dd voltage is above the preset low voltage value. the lvden bit is used to control the overall on/off function of the low voltage detector. setting the bit high will enable the low voltage detector. clearing the bit to zero will switch off the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 name lvdo lvden vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 lvdo: lvd output flag 0: no low voltage detected 1: low voltage detected bit 4 lvden: low voltage detector enable/disable 0: disable 1: enable bit 3 unimplemented, read as 0 bit 2~0 vlvd2~vlvd0: select lvd voltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v
rev. 1.00 170 ?a??? 1?? ?01? rev. 1.00 171 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom lvd operation the low voltage detector function operates by comparing the power supply voltage, v dd , with a pre-specifed voltage level stored in the lvdc register. this has a range of between 2.0v and 4.0v. when the power supply voltage, v dd , falls below this pre-determined value, the lvdo bit will be set high indicating a low power supply voltage condition. the low voltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the lvden bit is high. after enabling the low voltage detector, a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly, at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. lvd operation the low voltage detector also has its own interrupt which is contained within one of the multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the lvdo bit. the interrupt will only be generated after a delay of t lvd after the lvdo bit has been set high by a low voltage condition. when the device is powered down the low voltage detector will remain active if the lvden bit is high. in this case, the lvf interrupt request fag will be set, causing an interrupt to be generated if v dd falls below the preset lvd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low voltage detector wake up function is not required then the lvf fag should be frst set high before the device enters the sleep or idle mode. when lvd function is enabled, it is recommended to clear lvd fag frst, and then enables interrupt function to avoid mistake action.
rev. 1.00 17? ?a??? 1?? ?01? rev. 1.00 17? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom lcd driver for large volume applications, which incorporate an lcd in their design, the use of a custom display rather than a more expensive character based display reduces costs signifcantly. however, the corresponding com and seg signals required, which vary in both amplitude and time, to drive such a custom display require many special considerations for proper lcd operation to occur. these devices all contain an lcd driver function, which with their internal lcd signal generating circuitry and various options, will automatically generate these time and amplitude varying signals to provide a means of direct driving and easy interfacing to a range of custom lcds. all devices include a wide range of options to enable lcd displays of various types to be driven. the table shows the range of options available across the device range. device duty bias bias type wave type ht6?f?0a 1/? o? 1/4 1/? o? 1/? r o? c a o ? b ht6?f40a ht6?f50a lcd selections lcd memory an area of data memory is especially reserved for use for the lcd display data. this data area is known as the lcd memory. any data written here will be automatically read by the internal display driver circuits, which will in turn automatically generate the necessary lcd driving signals. therefore any data written into this memory will be immediately refected into the actual display connected to the microcontroller. as the lcd memory addresses overlap those of the general purpose data memory, it s stored in its own independent bank 1 area. the data memory bank to be used is chosen by using the bank pointer, which is a special function register in the data memory, with the name, bp. to access the lcd memory therefore requires frst that bank 1 is selected by writing a value of 01h to the bp register. after this, the memory can then be accessed by using indirect addressing through the use of memory pointer mp1. with bank 1 selected, then using mp1 to read or write to the memory area, starting with address 80h for all the devices, will result in operations to the lcd memory. directly addressing the display memory is not applicable and will result in a data access to the bank 0 general purpose data memory. the accompanying lcd memory map diagrams shows how the internal lcd memory is mapped to the segments and commons of the display for the devices. lcd memory maps for devices with smaller memory capacities can be extrapolated from these diagrams.
rev. 1.00 17? ?a??? 1?? ?01? rev. 1.00 17? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom co?0 co?? co?? co?1 seg0 seg?? seg?1 seg1 80h ?6h ?5h 81h seg?? ?7h co?0 co?? co?1 seg0 seg?? seg?1 seg1 80h ?6h ?5h 81h seg?4 seg?? ?8h ?7h b0 b1 b7 b6 b5 b4 b? b? 24 seg x 4 com b0 b1 b7 b6 b5 b4 b? b? 25 seg x 3 com : unused? ?ead as 0 ht69f30a lcd memory map co?0 co?? co?? co?1 seg0 seg?4 seg?? seg1 80h a?h a1h 81h seg?5 a?h co?0 co?? co?1 seg0 seg?4 seg?? seg1 80h a?h a1h 81h seg?6 seg?5 a4h a?h b0 b1 b7 b6 b5 b4 b? b? 36 seg x 4 com b0 b1 b7 b6 b5 b4 b? b? 37 seg x 3 com : unused? ?ead as 0" ht69f40a lcd memory map co?0 co?? co?? co?1 seg0 seg46 seg45 seg1 80h aeh adh 81h seg47 afh co?0 co?? co?1 seg0 seg46 seg45 seg1 80h aeh adh 81h seg48 seg47 b0h afh b0 b1 b7 b6 b5 b4 b? b? 48 seg x 4 com b0 b1 b7 b6 b5 b4 b? b? 49 seg x 3 com : unused? ?ead as 0 HT69F50A lcd memory map
rev. 1.00 174 ?a??? 1?? ?01? rev. 1.00 175 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom lcd register there is one control register, named as lcdc, in the data memory used to control the various setup features of the lcd driver. various bits in this registers control functions such as lcd wave type, duty type, bias type, bias resistor selection as well as overall lcd enable and disable. the lcden bit in the lcdc register, which provides the overall lcd enable/disable function, will only be effective when the device is in the noamrl, slow or idle mode. if the device is in the sleep mode then the display will always be disabled. bits, rsel0 and rsel1, in the lcdc register select the internal bias resistors to supply the lcd panel with the correct bias voltages. a choice to best match the lcd panel used in the application can be selected also to minimise bias current. the type bit in the same register is used to select whether type a or type b lcd control signals are used. lcdc register bit 7 6 5 4 3 2 1 0 name type dtyc bias rsel1 rsel0 lcden r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 type: lcd wave type control 0: type a 1: type b bit 6 unimplemented, read as 0 bit 5 dtyc: lcd duty control 0: 1/3 duty 1: 1/4 duty bit 4 unimplemented, read as 0 bit 3 bias: lcd bias control 0: 1/2 bias 1: 1/3 bias bit 2~1 rsel1~rsel0: lcd bias resistor selection 1/3 bias 00: 600k 01: 300k 10: 100k 11: 50k 1/2 bias 00: 400k 01: 200k 10: 67k 11: 34k bit 0 lcden: lcd enable control 0: disable 1: enable in the normal, slow or idle mode, the lcd on/off function can be controlled by this bit. in the sleep mode, the lcd function is always off.
rev. 1.00 174 ?a??? 1?? ?01? rev. 1.00 175 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom lcd reset function the lcd has an internal reset function that is an or function of the inverted lcden bit in the lcdc register and the sleep function. when the lcden bit is set to 1 to enable the lcd driver function before the device enters the sleep mode, the lcd function will be reset after the device enters the sleep mode. clearing the lcden bit to zero will also reset the lcd function. lcden sleep mode reset lcd 0 off 0 on 1 off x 1 on lcd reset function clock source the lcd clock source is the internal clock signal, f sub , divided by 8, using an internal divider circuit. the f sub internal clock is supplied by either the lirc or lxt oscillator, the choice of which is determined by a confguration option. for proper lcd operation, this arrangement is provided to generate an ideal lcd clock source frequency of 4khz. f sub clock source lcd clock frequency lirc 4khz lxt 4khz lcd clock source lcd driver output the number of com and seg outputs supplied by the lcd driver, as well as its biasing and duty selections, are dependent upon how the lcd control bits are programmed. the bias type, whether c or r type is selected via a confguration option. the nature of liquid crystal displays require that only ac voltages can be applied to their pixels as the application of dc voltages to lcd pixels may cause permanent damage. for this reason the relative contrast of an lcd display is controlled by the actual rms voltage applied to each pixel, which is equal to the rms value of the voltage on the com pin minus the voltage applied to the seg pin. this differential rms voltage must be greater than the lcd saturation voltage for the pixel to be on and less than the threshold voltage for the pixel to be off. the requirement to limit the dc voltage to zero and to control as many pixels as possible with a minimum number of connections, requires that both a time and amplitude signal is generated and applied to the application lcd. these time and amplitude varying signals are automatically generated by the lcd driver circuits in the microcontroller. what is known as the duty determines the number of common lines used, which are also known as backplanes or coms. the duty, which is chosen by a control bit to have a value of 1/3 or 1/4 and which equates to a com number of 3 or 4 respectively, therefore defines the number of time divisions within each lcd signal frame. two types of signal generation are also provided, known as type a and type b, the required type is selected via the type bit in the lcdc register. type b offers lower frequency signals, however lower frequencies may introduce fickering and infuence display clarity.
rev. 1.00 176 ?a??? 1?? ?01? rev. 1.00 177 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom lcd voltage source biasing the time and amplitude varying signals generated by the lcd driver function require the generation of several voltage levels for their operation. the number of voltage levels used by the signal depends upon the value of the bias bit in the lcdc register. the device can have either r type or c type biasing selected via a configuration option. selecting the c type biasing will enable an internal charge pump whose multiplier ratio can be selected using an additional confguration option. for r type biasing an external lcd voltage source must be supplied on pin vlcd to generate the internal biasing voltages. this could be the microcontroller power supply or some other voltage source. for the r type 1/2 bias selection, three voltage levels v ss , v a and v b are utilised. the voltage v a is equal to the externally supplied voltage source applied to pin vlcd. the voltage v b is generated internally by the microcontroller and will have a value equal to v lcd /2. for the r type 1/3 bias selection, four voltage levels v ss , v a , v b and v c are utilised. the voltage v a is equal to v lcd . the voltage v b is equal to v lcd 2/3 while the voltage v c is equal to v lcd 1/3. in addition to selecting 1/2 or 1/3 bias, several values of bias resistor can be chosen using bits in the lcdc register. different values of internal bias resistors can be selected using the rsel0 and resel1 bits in the lcdc register. this along with the voltage on pin vlcd will determine the bias current. the connection to the vmax pin depends upon the voltage that is applied to the vlcd pin. if the vdd voltage is greater than the voltage applied to the vlcd pin then the vmax pin should be connected to vdd, otherwise the vmax pin should be connected to pin vlcd. note that no external capacitors or resistors are required to be connected if r type biasing is used. condition vmax connection v dd > v lcd conne?t v?ax to vdd ot?e?wise conne?t v?ax to vlcd r type bias vmax pin connection for c type biasing an external lcd voltage source must also be supplied on pin vlcd to generate the internal biasing voltages. the c type biasing scheme uses an internal charge pump circuit, which in the case of the 1/3 bias selection, can generate voltages higher than what is supplied on vlcd. this feature is useful in applications where the microcontroller supply voltage is less than the supply voltage required by the lcd. an additional charge pump capacitor must also be connected between pins c1 and c2 to generate the necessary voltage levels. for the c type 1/2 bias selection, three voltage levels v ss , v a and v b are utilised. the voltage v a is generated internally and has a value of v lcd . the voltage v b will have a value equal to v a 1/2. for the c type 1/2 bias confguration v c is not used. for the c type 1/3 bias selection, four voltage levels v ss , v a , v b and v c are utilised. the voltage v a is generated internally and has a value of v lcd 3/2. the voltage v b will have a value equal to v a 2/3 and v c will have a value equal to v a 1/3. the connection to the vmax pin depends upon the bias and the voltage that is applied to vlcd. it is extremely important to ensure that these charge pump generated internal voltages do not exceed the maximum v dd voltage of 5.5v. biasing type vmax connection 1/? bias v dd >v lcd 1.5 conne?t v?ax to vdd ot?e?wise conne?t v?ax to v1 1/? bias v dd >v lcd conne?t v?ax to vdd ot?e?wise conne?t v?ax to vlcd c type bias vmax pin connection
rev. 1.00 176 ?a??? 1?? ?01? rev. 1.00 177 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom lcd waveform timing diagram the accompanying timing diagrams depict the display driver signals generated by the microcontroller for various values of duty and bias. the huge range of various permutations only permits a few types to be displayed here.

lcd driver output C type a- 1/3 duty, 1/2 bias note: for 1/2 bias, the v a =v lcd , v b =v lcd 1/2 for both r and c type.
rev. 1.00 178 ?a??? 1?? ?01? rev. 1.00 17? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom

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? ? ? ? ? ? ? ? ? ? lcd driver output C type a - 1/4 duty, 1/3 bias note: for 1/3 r type bias, the v a =v lcd , v b =v lcd 2/3 and v c =v lcd 1/3. for 1/3 c type bias, the v a =v lcd 1.5, v b =v lcd and v c =v lcd 1/2.
rev. 1.00 178 ?a??? 1?? ?01? rev. 1.00 17? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom

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lcd driver output C type a- 1/3 duty, 1/3 bias note: for 1/3 r type bias, the v a =v lcd , v b =v lcd 2/3 and v c =v lcd 1/3. for 1/3 c type bias, v a =v lcd 1.5, v b =v lcd and v c =v lcd 1/2.
rev. 1.00 180 ?a??? 1?? ?01? rev. 1.00 181 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom 1 f ra m e c o m 0 c o m 1 c o m 2 a l l s egm ent s a r e o f f c o m 0 s i de s egm ent s a r e o n c o m 1 s i d e s egm ent s a r e o n c o m 2 s i d e s egm ent s a r e o n ( o t her c o m b i n a t i ons a r e o m i tted) c o m 0 , 1 s i d e s egm ent s a r e o n n o r m a l o p e r a t i on m ode d u r i ng r ese t o r l cd o f f c o m 0 , c o m 1 , c o m 2 a l l s egm e n t out put s c o m 0 , 2 s i d e s egm ent s a r e o n v a v b v c v s s v a v b v c v s s v a v b v c v s s v a v b v c v s s v a v b v c v s s v a v b v c v s s v a v b v c v s s v a v b v c v s s v a v b v c v s s v a v b v c v s s v a v b v c v s s v a v b v c v s s a l l s egm ent s a r e o n lcd driver output C type b- 1/3 duty, 1/3 bias note: for 1/3 r type bias, the v a =v lcd , v b =v lcd 2/3 and v c =v lcd 1/3. for 1/3 c type bias, v a =v lcd 3/2, v b =v lcd and v c =v lcd 1/2.
rev. 1.00 180 ?a??? 1?? ?01? rev. 1.00 181 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom

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? ? ? ? ? ? ? ? ? ? va vb vc vss 1 f?ame va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss co?0 co?1 co?? all segments a?e off co?0 side segments a?e on co?? co?1 side segments a?e on co?? side segments a?e on (ot?e? ?ombinations a?e omitted) co?0? 1 side segments a?e on co?? side segments a?e on normal operation mode during reset or lcd off co?0? co?1? co??? co?? all segment outputs va vb vc vss va vb vc vss va vb vc vss co?0? ? side segments a?e on va vb vc vss co?0? ? side segments a?e on va vb vc vss all segments a?e on lcd driver output C type b- 1/4 duty, 1/3 bias note: for 1/3 r type bias, the v a =v lcd , v b =v lcd 2/3 and v c =v lcd 1/3. for 1/3 c type bias, v a =v lcd 3/2, v b =v lcd and v c =v lcd 1/2.
rev. 1.00 18? ?a??? 1?? ?01? rev. 1.00 18? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom programming considerations certain precautions must be taken when programming the lcd. one of these is to ensure that the lcd memory is properly initialised after the microcontroller is powered on. like the general purpose data memory, the contents of the lcd memory are in an unknown condition after power-on. as the contents of the lcd memory will be mapped into the actual display, it is important to initialise this memory area into a known condition soon after applying power to obtain a proper display pattern. consideration must also be given to the capacitive load of the actual lcd used in the application. as the load presented to the microcontroller by lcd pixels can be generally modeled as mainly capacitive in nature, it is important that this is not excessive, a point that is particularly true in the case of the com lines which may be connected to many lcd pixels. the accompanying diagram depicts the equivalent circuit of the lcd. one additional consideration that must be taken into account is what happens when the microcontroller enters the idle or slow mode. the lcden control bit in the lcdc register permits the display to be powered off to reduce power consumption. if this bit is zero, the driving signals to the display will cease, producing a blank display pattern but reducing any power consumption associated with the lcd. after power-on, note that as the lcden bit will be cleared to zero, the display function will be disabled. lcd panel equivalent circuit
rev. 1.00 18? ?a??? 1?? ?01? rev. 1.00 18? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom confguration options confguration options refer to certain options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. all options must be defned for proper system function, the details of which are shown in the table. no. options 1 hig? speed system os?illato? sele?tion C f h hxt ? erc? ec o? hirc ? hxt ?ode sele?tion 1?hz~1??hz o? 455khz ? low speed system os?illato? sele?tion C f l lxt o ? lirc 4 hirc f?equen?y sele?tion 4?hz? 8?hz o? 1??hz 5 lcd bias type sele ?tion r type o? c type 6 lcd voltage sele ?tion v lcd voltage is ?.0v ? 4.5v o? 1.5v 7 t? r/int pin input filte? fun?tion enable o? disable 8 i/o o? reset pin sele?tion reset pin o? i/o pin ? wat ?? dog time? fun?tion always enable o? appli?ation p?og?am enable note: the f sub clock source is derived from lxt or lirc selected by the f l confguration option.
rev. 1.00 184 ?a??? 1?? ?01? rev. 1.00 185 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom application circuits vdd pa7/ res vss p b0/ osc 1 p b1/ osc 2 p b2/ xt 1 p b3/ xt 2 osc circuit osc circuit lcd panel com [ 3: 0 ] seg [ 47: 0 ] vlcd vmax 100k 0 .1 uf 0 .1 uf 0 .1 uf 0 .1 uf c1 c2 v1 v2 0 .1 uf pa0/ int 1/ tck1 pa1/ tp0_1 pa2/ tck 0/ tck2 pa3/ tp2_0 pa4/ int0 pa5/ tp2_1 pa6/ tp0_0 pb4/ tp1a pb5/ tp1b_0 pb6/ tp1b_1 pb7/ tp1b_2 pc3~pc 6 p d0~pd7 pe 0~ p e7 pf 0~pf7 p g 0~p g 7 p h0~ph7 v dd
rev. 1.00 184 ?a??? 1?? ?01? rev. 1.00 185 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5s and branch or call instructions would be implemented within 1s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.00 186 ?a??? 1?? ?01? rev. 1.00 187 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is normally implemented by using registers. however, when working with large amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.00 186 ?a??? 1?? ?01? rev. 1.00 187 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a?[m] add data ?emo? y to acc 1 z? c? ac? ov add? a?[m] add acc to data ?emo?y 1 note z? c? ac? ov add a?x add immediate data to acc 1 z? c? ac? ov adc a?[m] add data ?emo? y to acc wit? ca??y 1 z? c? ac? ov adc? a?[m] add acc to data memo ?y wit? ca??y 1 note z? c? ac? ov sub a?x subt?a?t immediate data f?om t? e acc 1 z? c? ac? ov sub a?[m] subt?a?t data ?emo?y f? om acc 1 z? c? ac? ov sub? a?[m] subt?a?t data ?emo?y f? om acc wit? ?esult in data ?emo?y 1 note z? c? ac? ov sbc a?[m] subt?a?t data ?emo?y f? om acc wit? ca??y 1 z? c? ac? ov sbc? a?[m] subt?a?t data ?emo?y f? om acc wit? ca??y ? ?esult in data ?emo?y 1 note z? c? ac? ov daa [m] de? imal adjust acc fo? addition wit? ?esult in data ?emo?y 1 note c logic operation and a?[m] logi? al and data ?emo? y to acc 1 z or a?[m] logi?al or data ?emo? y to acc 1 z xor a?[m] logi?al xor data ?emo? y to acc 1 z and? a?[m] logi? al and acc to data ?emo?y 1 note z or? a?[m] logi? al or acc to data ?emo?y 1 note z xor? a?[m] logi? al xor acc to data ?emo?y 1 note z and a?x logi? al and immediate data to acc 1 z or a?x logi? al or immediate data to acc 1 z xor a?x logi? al xor immediate data to acc 1 z cpl [m] complement data ?emo?y 1 note z cpla [m] complement data ?emo?y wit? ? esult in acc 1 z increment & decrement inca [m] in??ement data ?emo?y wit? ? esult in acc 1 z inc [m] in??ement data ?emo?y 1 note z deca [m] de??ement data ?emo?y wit? ? esult in acc 1 z dec [m] de??ement data ?emo?y 1 note z rotate rra [m] rotate data ?emo?y ?ig?t wit? ? esult in acc 1 none rr [m] rotate data ?emo?y ?ig?t 1 note none rrca [m] rotate data ?emo?y ?ig?t t??oug? ca??y wit? ? esult in acc 1 c rrc [m] rotate data ?emo?y ?ig?t t??oug? ca??y 1 note c rla [m] rotate data ?emo?y left wit? ? esult in acc 1 none rl [m] rotate data ?emo?y left 1 note none rlca [m] rotate data ?emo?y left t??oug? ca??y wit? ? esult in acc 1 c rlc [m] rotate data ?emo?y left t??oug? ca??y 1 note c
rev. 1.00 188 ?a??? 1?? ?01? rev. 1.00 18? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom mnemonic description cycles flag affected data move ? ov a?[m] ?ove data ?emo? y to acc 1 none ?ov [m]?a ? ove acc to data ?emo?y 1 note none ? ov a?x ? ove immediate data to acc 1 none bit operation clr [m].i clea? bit of data ?emo?y 1 note none set [m].i set bit of data ?emo?y 1 note none branch j? p add? jump un?onditionally ? none sz [m] skip if data ?emo?y is ze?o 1 note none sza [m] skip if data ?emo?y is ze?o wit? data movement to acc 1 note none sz [m].i skip if bit i of data ?emo?y is ze?o 1 note none snz [m].i skip if bit i of data ?emo?y is not ze?o 1 note none siz [m] skip if in??ement data ?emo?y is ze?o 1 note none sdz [m] skip if de??ement data ?emo?y is ze?o 1 note none siza [m] skip if in??ement data ?emo?y is ze?o wit? ? esult in acc 1 note none sdza [m] skip if de??ement data ?emo?y is ze?o wit? ? esult in acc 1 note none call add ? sub?outine ?all ? none ret retu?n f?om sub?outine ? none ret a ?x retu?n f?om sub? outine and load immediate data to acc ? none reti retu?n f?om inte??upt ? none table read tabrdc [m] read table (?u?? ent page) to tblh and data ?emo?y ? note none tabrdl [m] read table (last page) to tblh and data ?emo?y ? note none miscellaneous nop no ope?ation 1 none clr [m] clea? data ?emo?y 1 note none set [m] set data ?emo?y 1 note none clr wdt clea? wat?? dog time? 1 to ? pdf clr wdt1 p?e-?lea? wat?? dog time? 1 to ? pdf clr wdt? p?e-?lea? wat?? dog time? 1 to ? pdf swap [m] swap nibbles of data ?emo?y 1 note none swapa [m] swap nibbles of data ?emo?y wit? ? esult in acc 1 none halt ente? powe? down mode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the "clr wdt1" and "clr wdt2" instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both "clr wdt1" and "clr wdt2" instructions are consecutively executed. otherwise the to and pdf fags remain unchanged.
rev. 1.00 188 ?a??? 1?? ?01? rev. 1.00 18? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom instruction defnition adc a,[m] add data memory to acc with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the accumulator. operation acc acc + [m] + c affected fag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the specifed data memory. operation [m] acc + [m] + c affected fag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specifed data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected fag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specifed immediate data are added. the result is stored in the accumulator. operation acc acc + x affected fag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specifed data memory and the accumulator are added. the result is stored in the specifed data memory. operation [m] acc + [m] affected fag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and [m] affected fag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specifed immediate data perform a bit wise logical and operation. the result is stored in the accumulator. operation acc acc and x affected fag(s) z andm a,[m] logical and acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical and operation. the result is stored in the data memory. operation [m] acc and [m] affected fag(s) z
rev. 1.00 1?0 ?a??? 1?? ?01? rev. 1.00 1?1 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom call addr subroutine call description unconditionally calls a subroutine at the specifed address. the program counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specifed address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruction. operation stack program counter + 1 program counter addr affected fag(s) none clr [m] clear data memory description each bit of the specifed data memory is cleared to 0. operation [m] 00h affected fag(s) none clr [m].i clear bit of data memory description bit i of the specifed data memory is cleared to 0. operation [m].i 0 affected fag(s) none clr wdt clear watchdog timer description the to, pdf fags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf fags and the wdt are all cleared. note that this instruction works in conjunction with clr wdt2 and must be executed alternately with clr wdt2 to have effect. repetitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf fags and the wdt are all cleared. note that this instruction works in conjunction with clr wdt1 and must be executed alternately with clr wdt1 to have effect. repetitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf cpl [m] complement data memory description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected fag(s) z
rev. 1.00 1?0 ?a??? 1?? ?01? rev. 1.00 1?1 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom cpla [m] complement data memory with result in acc description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected fag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd (binary coded decimal) value resulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac fag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c fag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by adding 00h, 06h, 60h or 66h depending on the accumulator and fag conditions. only the c fag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected fag(s) c dec [m] decrement data memory description data in the specifed data memory is decremented by 1. operation [m] [m] ? 1 affected fag(s) z deca [m] decrement data memory with result in acc description data in the specifed data memory is decremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] ? 1 affected fag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down fag pdf is set and the wdt time-out fag to is cleared. operation to 0 pdf 1 affected fag(s) to, pdf inc [m] increment data memory description data in the specifed data memory is incremented by 1. operation [m] [m] + 1 affected fag(s) z inca [m] increment data memory with result in acc description data in the specifed data memory is incremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] + 1 affected fag(s) z
rev. 1.00 1?? ?a??? 1?? ?01? rev. 1.00 1?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom jmp addr jump unconditionally description the contents of the program counter are replaced with the specifed address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected fag(s) none mov a,[m] move data memory to acc description the contents of the specifed data memory are copied to the accumulator. operation acc [m] affected fag(s) none mov a,x move immediate data to acc description the immediate data specifed is loaded into the accumulator. operation acc x affected fag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specifed data memory. operation [m] acc affected fag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected fag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or [m] affected fag(s) z or a,x logical or immediate data to acc description data in the accumulator and the specifed immediate data perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or x affected fag(s) z orm a,[m] logical or acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical or operation. the result is stored in the data memory. operation [m] acc or [m] affected fag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the restored address. operation program counter stack affected fag(s) none
rev. 1.00 1?? ?a??? 1?? ?01? rev. 1.00 1?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specifed immediate data. program execution continues at the restored address. operation program counter stack acc x affected fag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by setting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed before returning to the main program. operation program counter stack emi 1 affected fag(s) none rl [m] rotate data memory left description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 [m].7 affected fag(s) none rla [m] rotate data memory left with result in acc description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 [m].7 affected fag(s) none rlc [m] rotate data memory left through carry description the contents of the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 c c [m].7 affected fag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 c c [m].7 affected fag(s) c rr [m] rotate data memory right description the contents of the specifed data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 [m].0 affected fag(s) none
rev. 1.00 1?4 ?a??? 1?? ?01? rev. 1.00 1?5 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom rra [m] rotate data memory right with result in acc description data in the specifed data memory and the carry fag are rotated right by 1 bit with bit 0 rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 [m].0 affected fag(s) none rrc [m] rotate data memory right through carry description the contents of the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 c c [m].0 affected fag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 c c [m].0 affected fag(s) c sbc a,[m] subtract data memory from acc with carry description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] ? c affected fag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] ? c affected fag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specifed data memory are frst decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] ? 1 skip if [m]=0 affected fag(s) none
rev. 1.00 1?4 ?a??? 1?? ?01? rev. 1.00 1?5 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specifed data memory are frst decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] ? 1 skip if acc=0 affected fag(s) none set [m] set data memory description each bit of the specifed data memory is set to 1. operation [m] ffh affected fag(s) none set [m].i set bit of data memory description bit i of the specifed data memory is set to 1. operation [m].i 1 affected fag(s) none siz [m] skip if increment data memory is 0 description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] + 1 skip if [m]=0 affected fag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] + 1 skip if acc=0 affected fag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specifed data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected fag(s) none sub a,[m] subtract data memory from acc description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] affected fag(s) ov, z, ac, c
rev. 1.00 1?6 ?a??? 1?? ?01? rev. 1.00 1?7 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom subm a,[m] subtract data memory from acc with result in data memory description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] affected fag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specifed by the code is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? x affected fag(s) ov, z, ac, c swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specifed data memory are interchanged. operation [m].3~[m].0 ? [m].7~[m].4 affected fag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specifed data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected fag(s) none sz [m] skip if data memory is 0 description if the contents of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation skip if [m]=0 affected fag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specifed data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m]=0 affected fag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i=0 affected fag(s) none
rev. 1.00 1?6 ?a??? 1?? ?01? rev. 1.00 1?7 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none xor a,[m] logical xor data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor [m] affected fag(s) z xorm a,[m] logical xor acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical xor operation. the result is stored in the data memory. operation [m] acc xor [m] affected fag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specifed immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected fag(s) z
rev. 1.00 1?8 ?a??? 1?? ?01? rev. 1.00 1?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package information. additional supplementary information with regard to packaging is listed below. click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product tape and reel specifcations) ? packing meterials information ? carton information ? pb free products ? green packages products
rev. 1.00 1?8 ?a??? 1?? ?01? rev. 1.00 1?? ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom 48-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.?50 D 0.?58 b 0.?7? D 0.?80 c 0.?50 D 0.?58 d 0.?7? D 0.?80 e D 0.0?0 D f D 0.008 D g 0.05? D 0.057 h D D 0.06? i D 0.004 D j 0.018 D 0.0?0 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 8.?0 D ?.10 b 6.?0 D 7.10 c 8.?0 D ?.10 d 6.?0 D 7.10 e D 0.50 D f D 0.?0 D g 1.?5 D 1.45 h D D 1.60 i D 0.10 D j 0.45 D 0.75 k 0.10 D 0.?0 0 D 7
rev. 1.00 ?00 ?a??? 1?? ?01? rev. 1.00 ?01 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom 64-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.?50 D 0.?58 b 0.?7? D 0.?80 c 0.?50 D 0.?58 d 0.?7? D 0.?80 e D 0.016 D f 0.005 D 0.00? g 0.05? D 0.057 h D D 0.06? i 0.00? D 0.006 j 0.018 D 0.0?0 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 8.?0 D ?.10 b 6.?0 D 7.10 c 8.?0 D ?.10 d 6.?0 D 7.10 e D 0.40 D f 0.1? D 0.?? g 1.?5 D 1.45 h D D 1.60 i 0.05 D 0.15 j 0.45 D 0.75 k 0.0? D 0.?0 0 D 7
rev. 1.00 ?00 ?a??? 1?? ?01? rev. 1.00 ?01 ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom 80-pin lqfp (10mm10mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.46? D 0.476 b 0.??0 D 0.??8 c 0.46? D 0.476 d 0.??0 D 0.??8 e D 0.016 D f D 0.006 D g 0.05? D 0.057 h D D 0.06? i D 0.004 D j 0.018 D 0.0?0 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 11. ?0 D 1?.10 b ?.?0 D 10.10 c 11. ?0 D 1?.10 d ?.?0 D 10.10 e D 0.40 D f D 0.16 D g 1.?5 D 1.45 h D D 1.60 i D 0.10 D j 0.45 D 0.75 k 0.10 D 0.?0 0 D 7
rev. 1.00 ?0? ?a??? 1?? ?01? rev. 1.00 pb ?a??? 1?? ?01? ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom ht69f30a/ht69f40a/HT69F50A tinypower tm i/o flash 8-bit mcu with lcd & eeprom holtek semiconductor inc. (headquarters) no.?? c?eation rd. ii? s?ien?e pa?k? hsin??u? taiwan tel: 886- ?-56?-1??? fax: 886-?-56? -118? ? ttp://www.?oltek.?om.tw holtek semiconductor inc. (taipei sales offce) 4f-?? no. ?-?? yuanqu st.? nankang softwa?e pa?k? taipei 115? taiwan tel: 886- ?-?655-7070 fax: 886-?-?655-7?7? fax: 886-?-?655-7?8? (inte?national sales ?otline) holtek semiconductor (china) inc. (dongguan sales offce) building no.10? xinz?u cou?t? (no.1 headqua?te?s)? 4 cuiz?u road? songs?an lake? dongguan? c?ina 5??808 tel: 86-76 ?-?6?6-1?00 fax: 86-76?-?6?6-1? 11? 86-76?-?6?6-1??? holtek semiconductor (usa), inc. (north america sales offce) 467?? f?emont blvd.? f?emont? ca ?45?8? usa tel: 1-510- ?5?-?880 fax: 1-510-?5?-?885 ? ttp://www.?oltek.?om copy?ig?t ? ?01? by holtek se? iconductor inc. t ? e info? mation appea?ing in t ? is data s? eet is believed to be a??u? ate at t ? e time of publi? ation. howeve ?? holtek assumes no ? esponsibility a ? ising f ? om t ? e use of t ? e spe? ifi ? ations des ?? ibed. t?e appli?ations mentioned ?e?ein a?e used solely fo? t?e pu?pose of illust? ation and holtek makes no wa?? anty o? ?ep? esentation t ? at su?? appli? ations will be suitable wit ? out fu?t ?e? modifi? ation? no? ?e? ommends t? e use of its p?odu? ts fo? appli? ation t? at may p? esent a ? isk to ? uman life due to malfun?tion o? ot?e?wise. holtek's p?odu?ts a?e not aut?o?ized fo? use as ??iti?al ? omponents in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for t?e most up-to-date info?mation? please visit ou? web site at ? ttp://www.?oltek.?om.tw .

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